diff options
| author | Andrey Smirnov <andrew.smirnov@gmail.com> | 2019-08-05 11:57:00 -0700 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-09-04 12:43:51 +0200 |
| commit | f7ec1721b38c82089b1bbd92f828cb615557cbc5 (patch) | |
| tree | 547d4be2aaf402bfc8429ac2b9ca3887425d79fc /drivers | |
| parent | 352bd55e5dce57176122693c80b1805e9db89b1e (diff) | |
tty: serial: fsl_lpuart: Don't enable TIE in .startup() or .resume()
Enabling TIE in .startup() callback causes the driver to start (or at
least try) to transmit data before .start_tx() is called. Which, while
harmless (since TIE handler will immediately disable it), is a no-op
and shouldn't really happen. Drop UARTCR2_TIE from list of bits set in
lpuart_startup().
This change will also not enable TIE in .resume(), but it seems that,
similart to .startup(), transmit interrupt shouldn't be enabled there
either.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Cory Tusar <cory.tusar@zii.aero>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Jiri Slaby <jslaby@suse.com>
Cc: linux-imx@nxp.com
Cc: linux-serial@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Link: https://lore.kernel.org/r/20190805185701.22863-6-andrew.smirnov@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/tty/serial/fsl_lpuart.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c index fb9961edce3a..5c3cc1051aa8 100644 --- a/drivers/tty/serial/fsl_lpuart.c +++ b/drivers/tty/serial/fsl_lpuart.c @@ -1410,7 +1410,7 @@ static void lpuart_setup_watermark_enable(struct lpuart_port *sport) lpuart_setup_watermark(sport); cr2 = readb(sport->port.membase + UARTCR2); - cr2 |= UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE; + cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE; writeb(cr2, sport->port.membase + UARTCR2); } |