diff options
| author | Joseph Lo <josephl@nvidia.com> | 2019-05-29 16:21:33 +0800 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2020-05-12 22:48:41 +0200 |
| commit | cd4d6f357545bc03112265b19e5ed50592812986 (patch) | |
| tree | c5c1e23047f2282d4b60353255a367d6b040964b /drivers | |
| parent | 3dcbd36fa34ce9124ec51accd835130251f74213 (diff) | |
clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210
Introduce the low jitter path of PLLP and PLLMB which can be used as EMC
clock source.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra210.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index defe3b7ebfa4..57d97e87d870 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -3153,6 +3153,17 @@ static void __init tegra210_pll_init(void __iomem *clk_base, clk_register_clkdev(clk, "pll_m_ud", NULL); clks[TEGRA210_CLK_PLL_M_UD] = clk; + /* PLLMB_UD */ + clk = clk_register_fixed_factor(NULL, "pll_mb_ud", "pll_mb", + CLK_SET_RATE_PARENT, 1, 1); + clk_register_clkdev(clk, "pll_mb_ud", NULL); + clks[TEGRA210_CLK_PLL_MB_UD] = clk; + + /* PLLP_UD */ + clk = clk_register_fixed_factor(NULL, "pll_p_ud", "pll_p", + 0, 1, 1); + clks[TEGRA210_CLK_PLL_P_UD] = clk; + /* PLLU_VCO */ if (!tegra210_init_pllu()) { clk = clk_register_fixed_rate(NULL, "pll_u_vco", "pll_ref", 0, |