diff options
| author | Rex Zhu <Rex.Zhu@amd.com> | 2018-05-17 20:21:42 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-05-18 16:08:30 -0500 |
| commit | cd3cb7c08754cd5dd1cbccfc2296d6b7dde511f2 (patch) | |
| tree | c6e3a6dc0281bf551a0435356b228566e90107b4 /drivers | |
| parent | 5326c4525d1b2d5f1519268dd305e19c9bd4ef56 (diff) | |
drm/amd/pp: Fix build warning in vegam
warning: missing braces around initializer [-Wmissing-braces]
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c | 4 |
2 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c index cf99c5eaf080..ec38c9f50a4d 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c @@ -320,7 +320,7 @@ int atomctrl_get_memory_pll_dividers_ai(struct pp_hwmgr *hwmgr, pp_atomctrl_memory_clock_param_ai *mpll_param) { struct amdgpu_device *adev = hwmgr->adev; - COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3 mpll_parameters = {0}; + COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3 mpll_parameters = {{0}, 0, 0}; int result; mpll_parameters.ulClock.ulClock = cpu_to_le32(clock_value); diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c index c9a563399330..a40f7141131c 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c @@ -1366,10 +1366,12 @@ static int vegam_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) { struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend); struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend); - struct SMU75_Discrete_MCArbDramTimingTable arb_regs = {0}; + struct SMU75_Discrete_MCArbDramTimingTable arb_regs; uint32_t i, j; int result = 0; + memset(&arb_regs, 0, sizeof(SMU75_Discrete_MCArbDramTimingTable)); + for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) { for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) { result = vegam_populate_memory_timing_parameters(hwmgr, |