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authorChinh T Cao <chinh.t.cao@intel.com>2020-05-15 17:51:21 -0700
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2020-05-31 03:41:29 -0700
commitbff185e2406e10d2608857171537645714bea1f4 (patch)
treea47100e1851a3adb593f48dc3790018425135cdd /drivers
parentc9a12d6d2091175fe2dc1707dd40d6ad781414fe (diff)
ice: Update ICE_PHY_TYPE_HIGH_MAX_INDEX value
As currently, we are supporting only 5 PHY_SPEEDs for phy_type_high. Thus, we should adjust the value of ICE_PHY_TYPE_HIGH_MAX_INDEX to 5. Signed-off-by: Chinh T Cao <chinh.t.cao@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/ethernet/intel/ice/ice_adminq_cmd.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
index f04c338fb6e0..50040c5c55ec 100644
--- a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
+++ b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
@@ -974,7 +974,7 @@ struct ice_aqc_get_phy_caps {
#define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
#define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
#define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
-#define ICE_PHY_TYPE_HIGH_MAX_INDEX 19
+#define ICE_PHY_TYPE_HIGH_MAX_INDEX 5
struct ice_aqc_get_phy_caps_data {
__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */