drm/nouveau/dma: cosmetic changes

This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

5 files changed, 91 insertions, 91 deletions

diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/dmaobj.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/dmaobj.h
index c4fce8afcf83..2c3cc61adb74 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/dmaobj.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/dmaobj.h
@@ -12,7 +12,7 @@ struct nvkm_dmaobj {
 };
 
 struct nvkm_dmaeng {
-	struct nvkm_engine base;
+	struct nvkm_engine engine;
 
 	/* creates a "physical" dma object from a struct nvkm_dmaobj */
 	int (*bind)(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf100.c
index f880e5167e45..db7978ac6acb 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf100.c
@@ -30,17 +30,17 @@
 #include <nvif/class.h>
 #include <nvif/unpack.h>
 
-struct gf100_dmaobj_priv {
+struct gf100_dmaobj {
 	struct nvkm_dmaobj base;
 	u32 flags0;
 	u32 flags5;
 };
 
 static int
-gf100_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent,
+gf100_dmaobj_bind(struct nvkm_dmaobj *obj, struct nvkm_object *parent,
 		  struct nvkm_gpuobj **pgpuobj)
 {
-	struct gf100_dmaobj_priv *priv = (void *)dmaobj;
+	struct gf100_dmaobj *dmaobj = container_of(obj, typeof(*dmaobj), base);
 	int ret;
 
 	if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
@@ -57,13 +57,13 @@ gf100_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent,
 
 	ret = nvkm_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
 	if (ret == 0) {
-		nv_wo32(*pgpuobj, 0x00, priv->flags0 | nv_mclass(dmaobj));
-		nv_wo32(*pgpuobj, 0x04, lower_32_bits(priv->base.limit));
-		nv_wo32(*pgpuobj, 0x08, lower_32_bits(priv->base.start));
-		nv_wo32(*pgpuobj, 0x0c, upper_32_bits(priv->base.limit) << 24 |
-					upper_32_bits(priv->base.start));
+		nv_wo32(*pgpuobj, 0x00, dmaobj->flags0 | nv_mclass(dmaobj));
+		nv_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit));
+		nv_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start));
+		nv_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 |
+					upper_32_bits(dmaobj->base.start));
 		nv_wo32(*pgpuobj, 0x10, 0x00000000);
-		nv_wo32(*pgpuobj, 0x14, priv->flags5);
+		nv_wo32(*pgpuobj, 0x14, dmaobj->flags5);
 	}
 
 	return ret;
@@ -78,12 +78,12 @@ gf100_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 	union {
 		struct gf100_dma_v0 v0;
 	} *args;
-	struct gf100_dmaobj_priv *priv;
+	struct gf100_dmaobj *dmaobj;
 	u32 kind, user, unkn;
 	int ret;
 
-	ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
-	*pobject = nv_object(priv);
+	ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &dmaobj);
+	*pobject = nv_object(dmaobj);
 	if (ret)
 		return ret;
 	args = data;
@@ -97,7 +97,7 @@ gf100_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 		unkn = 0;
 	} else
 	if (size == 0) {
-		if (priv->base.target != NV_MEM_TARGET_VM) {
+		if (dmaobj->base.target != NV_MEM_TARGET_VM) {
 			kind = GF100_DMA_V0_KIND_PITCH;
 			user = GF100_DMA_V0_PRIV_US;
 			unkn = 2;
@@ -111,39 +111,39 @@ gf100_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 
 	if (user > 2)
 		return -EINVAL;
-	priv->flags0 |= (kind << 22) | (user << 20);
-	priv->flags5 |= (unkn << 16);
+	dmaobj->flags0 |= (kind << 22) | (user << 20);
+	dmaobj->flags5 |= (unkn << 16);
 
-	switch (priv->base.target) {
+	switch (dmaobj->base.target) {
 	case NV_MEM_TARGET_VM:
-		priv->flags0 |= 0x00000000;
+		dmaobj->flags0 |= 0x00000000;
 		break;
 	case NV_MEM_TARGET_VRAM:
-		priv->flags0 |= 0x00010000;
+		dmaobj->flags0 |= 0x00010000;
 		break;
 	case NV_MEM_TARGET_PCI:
-		priv->flags0 |= 0x00020000;
+		dmaobj->flags0 |= 0x00020000;
 		break;
 	case NV_MEM_TARGET_PCI_NOSNOOP:
-		priv->flags0 |= 0x00030000;
+		dmaobj->flags0 |= 0x00030000;
 		break;
 	default:
 		return -EINVAL;
 	}
 
-	switch (priv->base.access) {
+	switch (dmaobj->base.access) {
 	case NV_MEM_ACCESS_VM:
 		break;
 	case NV_MEM_ACCESS_RO:
-		priv->flags0 |= 0x00040000;
+		dmaobj->flags0 |= 0x00040000;
 		break;
 	case NV_MEM_ACCESS_WO:
 	case NV_MEM_ACCESS_RW:
-		priv->flags0 |= 0x00080000;
+		dmaobj->flags0 |= 0x00080000;
 		break;
 	}
 
-	return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
+	return dmaeng->bind(&dmaobj->base, nv_object(dmaobj), (void *)pobject);
 }
 
 static struct nvkm_ofuncs
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf110.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf110.c
index bf8f0f20976c..76063249853c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf110.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/gf110.c
@@ -30,16 +30,16 @@
 #include <nvif/class.h>
 #include <nvif/unpack.h>
 
-struct gf110_dmaobj_priv {
+struct gf110_dmaobj {
 	struct nvkm_dmaobj base;
 	u32 flags0;
 };
 
 static int
-gf110_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent,
+gf110_dmaobj_bind(struct nvkm_dmaobj *obj, struct nvkm_object *parent,
 		  struct nvkm_gpuobj **pgpuobj)
 {
-	struct gf110_dmaobj_priv *priv = (void *)dmaobj;
+	struct gf110_dmaobj *dmaobj = container_of(obj, typeof(*dmaobj), base);
 	int ret;
 
 	if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
@@ -63,9 +63,9 @@ gf110_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent,
 
 	ret = nvkm_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
 	if (ret == 0) {
-		nv_wo32(*pgpuobj, 0x00, priv->flags0);
-		nv_wo32(*pgpuobj, 0x04, priv->base.start >> 8);
-		nv_wo32(*pgpuobj, 0x08, priv->base.limit >> 8);
+		nv_wo32(*pgpuobj, 0x00, dmaobj->flags0);
+		nv_wo32(*pgpuobj, 0x04, dmaobj->base.start >> 8);
+		nv_wo32(*pgpuobj, 0x08, dmaobj->base.limit >> 8);
 		nv_wo32(*pgpuobj, 0x0c, 0x00000000);
 		nv_wo32(*pgpuobj, 0x10, 0x00000000);
 		nv_wo32(*pgpuobj, 0x14, 0x00000000);
@@ -83,12 +83,12 @@ gf110_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 	union {
 		struct gf110_dma_v0 v0;
 	} *args;
-	struct gf110_dmaobj_priv *priv;
+	struct gf110_dmaobj *dmaobj;
 	u32 kind, page;
 	int ret;
 
-	ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
-	*pobject = nv_object(priv);
+	ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &dmaobj);
+	*pobject = nv_object(dmaobj);
 	if (ret)
 		return ret;
 	args = data;
@@ -101,7 +101,7 @@ gf110_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 		page = args->v0.page;
 	} else
 	if (size == 0) {
-		if (priv->base.target != NV_MEM_TARGET_VM) {
+		if (dmaobj->base.target != NV_MEM_TARGET_VM) {
 			kind = GF110_DMA_V0_KIND_PITCH;
 			page = GF110_DMA_V0_PAGE_SP;
 		} else {
@@ -113,11 +113,11 @@ gf110_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 
 	if (page > 1)
 		return -EINVAL;
-	priv->flags0 = (kind << 20) | (page << 6);
+	dmaobj->flags0 = (kind << 20) | (page << 6);
 
-	switch (priv->base.target) {
+	switch (dmaobj->base.target) {
 	case NV_MEM_TARGET_VRAM:
-		priv->flags0 |= 0x00000009;
+		dmaobj->flags0 |= 0x00000009;
 		break;
 	case NV_MEM_TARGET_VM:
 	case NV_MEM_TARGET_PCI:
@@ -132,7 +132,7 @@ gf110_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 		return -EINVAL;
 	}
 
-	return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
+	return dmaeng->bind(&dmaobj->base, nv_object(dmaobj), (void *)pobject);
 }
 
 static struct nvkm_ofuncs
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c
index a6bfd0894f58..21c5c90b06a8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv04.c
@@ -29,7 +29,7 @@
 
 #include <nvif/class.h>
 
-struct nv04_dmaobj_priv {
+struct nv04_dmaobj {
 	struct nvkm_dmaobj base;
 	bool clone;
 	u32 flags0;
@@ -37,14 +37,14 @@ struct nv04_dmaobj_priv {
 };
 
 static int
-nv04_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent,
+nv04_dmaobj_bind(struct nvkm_dmaobj *obj, struct nvkm_object *parent,
 		 struct nvkm_gpuobj **pgpuobj)
 {
-	struct nv04_dmaobj_priv *priv = (void *)dmaobj;
+	struct nv04_dmaobj *dmaobj = container_of(obj, typeof(*dmaobj), base);
 	struct nvkm_gpuobj *gpuobj;
-	u64 offset = priv->base.start & 0xfffff000;
-	u64 adjust = priv->base.start & 0x00000fff;
-	u32 length = priv->base.limit - priv->base.start;
+	u64 offset = dmaobj->base.start & 0xfffff000;
+	u64 adjust = dmaobj->base.start & 0x00000fff;
+	u32 length = dmaobj->base.limit - dmaobj->base.start;
 	int ret;
 
 	if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
@@ -59,10 +59,10 @@ nv04_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent,
 		}
 	}
 
-	if (priv->clone) {
+	if (dmaobj->clone) {
 		struct nv04_mmu *mmu = nv04_mmu(dmaobj);
 		struct nvkm_gpuobj *pgt = mmu->vm->pgt[0].obj[0];
-		if (!dmaobj->start)
+		if (!dmaobj->base.start)
 			return nvkm_gpuobj_dup(parent, pgt, pgpuobj);
 		offset  = nv_ro32(pgt, 8 + (offset >> 10));
 		offset &= 0xfffff000;
@@ -71,10 +71,10 @@ nv04_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent,
 	ret = nvkm_gpuobj_new(parent, parent, 16, 16, 0, &gpuobj);
 	*pgpuobj = gpuobj;
 	if (ret == 0) {
-		nv_wo32(*pgpuobj, 0x00, priv->flags0 | (adjust << 20));
+		nv_wo32(*pgpuobj, 0x00, dmaobj->flags0 | (adjust << 20));
 		nv_wo32(*pgpuobj, 0x04, length);
-		nv_wo32(*pgpuobj, 0x08, priv->flags2 | offset);
-		nv_wo32(*pgpuobj, 0x0c, priv->flags2 | offset);
+		nv_wo32(*pgpuobj, 0x08, dmaobj->flags2 | offset);
+		nv_wo32(*pgpuobj, 0x0c, dmaobj->flags2 | offset);
 	}
 
 	return ret;
@@ -87,50 +87,50 @@ nv04_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 {
 	struct nvkm_dmaeng *dmaeng = (void *)engine;
 	struct nv04_mmu *mmu = nv04_mmu(engine);
-	struct nv04_dmaobj_priv *priv;
+	struct nv04_dmaobj *dmaobj;
 	int ret;
 
-	ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
-	*pobject = nv_object(priv);
+	ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &dmaobj);
+	*pobject = nv_object(dmaobj);
 	if (ret || (ret = -ENOSYS, size))
 		return ret;
 
-	if (priv->base.target == NV_MEM_TARGET_VM) {
+	if (dmaobj->base.target == NV_MEM_TARGET_VM) {
 		if (nv_object(mmu)->oclass == &nv04_mmu_oclass)
-			priv->clone = true;
-		priv->base.target = NV_MEM_TARGET_PCI;
-		priv->base.access = NV_MEM_ACCESS_RW;
+			dmaobj->clone = true;
+		dmaobj->base.target = NV_MEM_TARGET_PCI;
+		dmaobj->base.access = NV_MEM_ACCESS_RW;
 	}
 
-	priv->flags0 = nv_mclass(priv);
-	switch (priv->base.target) {
+	dmaobj->flags0 = nv_mclass(dmaobj);
+	switch (dmaobj->base.target) {
 	case NV_MEM_TARGET_VRAM:
-		priv->flags0 |= 0x00003000;
+		dmaobj->flags0 |= 0x00003000;
 		break;
 	case NV_MEM_TARGET_PCI:
-		priv->flags0 |= 0x00023000;
+		dmaobj->flags0 |= 0x00023000;
 		break;
 	case NV_MEM_TARGET_PCI_NOSNOOP:
-		priv->flags0 |= 0x00033000;
+		dmaobj->flags0 |= 0x00033000;
 		break;
 	default:
 		return -EINVAL;
 	}
 
-	switch (priv->base.access) {
+	switch (dmaobj->base.access) {
 	case NV_MEM_ACCESS_RO:
-		priv->flags0 |= 0x00004000;
+		dmaobj->flags0 |= 0x00004000;
 		break;
 	case NV_MEM_ACCESS_WO:
-		priv->flags0 |= 0x00008000;
+		dmaobj->flags0 |= 0x00008000;
 	case NV_MEM_ACCESS_RW:
-		priv->flags2 |= 0x00000002;
+		dmaobj->flags2 |= 0x00000002;
 		break;
 	default:
 		return -EINVAL;
 	}
 
-	return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
+	return dmaeng->bind(&dmaobj->base, nv_object(dmaobj), (void *)pobject);
 }
 
 static struct nvkm_ofuncs
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv50.c
index 4d3c828fe0e6..6aa18884184e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/nv50.c
@@ -30,17 +30,17 @@
 #include <nvif/class.h>
 #include <nvif/unpack.h>
 
-struct nv50_dmaobj_priv {
+struct nv50_dmaobj {
 	struct nvkm_dmaobj base;
 	u32 flags0;
 	u32 flags5;
 };
 
 static int
-nv50_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent,
+nv50_dmaobj_bind(struct nvkm_dmaobj *obj, struct nvkm_object *parent,
 		 struct nvkm_gpuobj **pgpuobj)
 {
-	struct nv50_dmaobj_priv *priv = (void *)dmaobj;
+	struct nv50_dmaobj *dmaobj = container_of(obj, typeof(*dmaobj), base);
 	int ret;
 
 	if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
@@ -69,13 +69,13 @@ nv50_dmaobj_bind(struct nvkm_dmaobj *dmaobj, struct nvkm_object *parent,
 
 	ret = nvkm_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);
 	if (ret == 0) {
-		nv_wo32(*pgpuobj, 0x00, priv->flags0 | nv_mclass(dmaobj));
-		nv_wo32(*pgpuobj, 0x04, lower_32_bits(priv->base.limit));
-		nv_wo32(*pgpuobj, 0x08, lower_32_bits(priv->base.start));
-		nv_wo32(*pgpuobj, 0x0c, upper_32_bits(priv->base.limit) << 24 |
-					upper_32_bits(priv->base.start));
+		nv_wo32(*pgpuobj, 0x00, dmaobj->flags0 | nv_mclass(dmaobj));
+		nv_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit));
+		nv_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start));
+		nv_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 |
+					upper_32_bits(dmaobj->base.start));
 		nv_wo32(*pgpuobj, 0x10, 0x00000000);
-		nv_wo32(*pgpuobj, 0x14, priv->flags5);
+		nv_wo32(*pgpuobj, 0x14, dmaobj->flags5);
 	}
 
 	return ret;
@@ -90,12 +90,12 @@ nv50_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 	union {
 		struct nv50_dma_v0 v0;
 	} *args;
-	struct nv50_dmaobj_priv *priv;
+	struct nv50_dmaobj *dmaobj;
 	u32 user, part, comp, kind;
 	int ret;
 
-	ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv);
-	*pobject = nv_object(priv);
+	ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &dmaobj);
+	*pobject = nv_object(dmaobj);
 	if (ret)
 		return ret;
 	args = data;
@@ -112,7 +112,7 @@ nv50_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 		kind = args->v0.kind;
 	} else
 	if (size == 0) {
-		if (priv->base.target != NV_MEM_TARGET_VM) {
+		if (dmaobj->base.target != NV_MEM_TARGET_VM) {
 			user = NV50_DMA_V0_PRIV_US;
 			part = NV50_DMA_V0_PART_256;
 			comp = NV50_DMA_V0_COMP_NONE;
@@ -128,41 +128,41 @@ nv50_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 
 	if (user > 2 || part > 2 || comp > 3 || kind > 0x7f)
 		return -EINVAL;
-	priv->flags0 = (comp << 29) | (kind << 22) | (user << 20);
-	priv->flags5 = (part << 16);
+	dmaobj->flags0 = (comp << 29) | (kind << 22) | (user << 20);
+	dmaobj->flags5 = (part << 16);
 
-	switch (priv->base.target) {
+	switch (dmaobj->base.target) {
 	case NV_MEM_TARGET_VM:
-		priv->flags0 |= 0x00000000;
+		dmaobj->flags0 |= 0x00000000;
 		break;
 	case NV_MEM_TARGET_VRAM:
-		priv->flags0 |= 0x00010000;
+		dmaobj->flags0 |= 0x00010000;
 		break;
 	case NV_MEM_TARGET_PCI:
-		priv->flags0 |= 0x00020000;
+		dmaobj->flags0 |= 0x00020000;
 		break;
 	case NV_MEM_TARGET_PCI_NOSNOOP:
-		priv->flags0 |= 0x00030000;
+		dmaobj->flags0 |= 0x00030000;
 		break;
 	default:
 		return -EINVAL;
 	}
 
-	switch (priv->base.access) {
+	switch (dmaobj->base.access) {
 	case NV_MEM_ACCESS_VM:
 		break;
 	case NV_MEM_ACCESS_RO:
-		priv->flags0 |= 0x00040000;
+		dmaobj->flags0 |= 0x00040000;
 		break;
 	case NV_MEM_ACCESS_WO:
 	case NV_MEM_ACCESS_RW:
-		priv->flags0 |= 0x00080000;
+		dmaobj->flags0 |= 0x00080000;
 		break;
 	default:
 		return -EINVAL;
 	}
 
-	return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject);
+	return dmaeng->bind(&dmaobj->base, nv_object(dmaobj), (void *)pobject);
 }
 
 static struct nvkm_ofuncs