diff options
| author | Nathan Chancellor <natechancellor@gmail.com> | 2019-02-01 13:12:26 -0700 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-02-05 21:15:32 -0500 |
| commit | 8daa12182a7ab441a2b3eeb170f9d8a12b206d6c (patch) | |
| tree | 1cbd292f07fc6b422408447c73c1e0d83f796c5d /drivers | |
| parent | 19afd79951e6303dbe0d15293a2f66ceb4c772f6 (diff) | |
drm/amd/display: Use memset to initialize variables in fill_plane_dcc_attributes
Clang warns:
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:2314:38:
warning: suggest braces around initialization of subobject
[-Wmissing-braces]
struct dc_surface_dcc_cap output = {0};
^
{}
Previous efforts to fix this type of warning by adding or removing
braces have been met with some pushback in favor of using memset [1][2].
Do that here, mirroring commit 05794eff1aa6 ("drm/amdgpu/gmc: fix
compiler errors [-Werror,-Wmissing-braces] (V2)") in this tree.
[1]: https://lore.kernel.org/lkml/022e41c0-8465-dc7a-a45c-64187ecd9684@amd.com/
[2]: https://lore.kernel.org/lkml/20181128.215241.702406654469517539.davem@davemloft.net/
Fixes: 7df7e505e82a ("drm/amd/display: Set requested plane state DCC params for GFX9")
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 640ac9d9f04f..a08820f86f0f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2297,12 +2297,15 @@ static bool fill_plane_dcc_attributes(struct amdgpu_device *adev, uint64_t info) { struct dc *dc = adev->dm.dc; - struct dc_dcc_surface_param input = {0}; - struct dc_surface_dcc_cap output = {0}; + struct dc_dcc_surface_param input; + struct dc_surface_dcc_cap output; uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B); uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0; uint64_t dcc_address; + memset(&input, 0, sizeof(input)); + memset(&output, 0, sizeof(output)); + if (!offset) return false; |