diff options
| author | Felix Fietkau <nbd@nbd.name> | 2019-07-03 21:32:10 +0200 |
|---|---|---|
| committer | Felix Fietkau <nbd@nbd.name> | 2019-09-05 17:42:28 +0200 |
| commit | 5f3413fc5e0106fc91b50c18c6e17ee130693282 (patch) | |
| tree | 5716f2887c902688a6d3be2e2c5618cce26591d2 /drivers | |
| parent | 592ed85d6b280081dda76e77e103bd7e68d2fb2f (diff) | |
mt76: mt7615: reset rate index/counters on rate table update
These values must be initialized to zero, otherwise the hardware could
reuse previous values, especially the rate index
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/wireless/mediatek/mt76/mt7615/mac.c | 5 | ||||
| -rw-r--r-- | drivers/net/wireless/mediatek/mt76/mt7615/regs.h | 4 |
2 files changed, 8 insertions, 1 deletions
diff --git a/drivers/net/wireless/mediatek/mt76/mt7615/mac.c b/drivers/net/wireless/mediatek/mt76/mt7615/mac.c index 49c14eb008d7..b896d8ce9e72 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7615/mac.c +++ b/drivers/net/wireless/mediatek/mt76/mt7615/mac.c @@ -501,7 +501,10 @@ void mt7615_mac_set_rates(struct mt7615_dev *dev, struct mt7615_sta *sta, w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, bw); w5 = mt76_rr(dev, addr + 5 * 4); - w5 &= ~(MT_WTBL_W5_BW_CAP | MT_WTBL_W5_CHANGE_BW_RATE); + w5 &= ~(MT_WTBL_W5_BW_CAP | MT_WTBL_W5_CHANGE_BW_RATE | + MT_WTBL_W5_MPDU_OK_COUNT | + MT_WTBL_W5_MPDU_FAIL_COUNT | + MT_WTBL_W5_RATE_IDX); w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, bw) | FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE, bw_idx ? bw_idx - 1 : 7); diff --git a/drivers/net/wireless/mediatek/mt76/mt7615/regs.h b/drivers/net/wireless/mediatek/mt76/mt7615/regs.h index 70e5ace33cc3..ea40581dc870 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7615/regs.h +++ b/drivers/net/wireless/mediatek/mt76/mt7615/regs.h @@ -181,6 +181,10 @@ #define MT_WTBL_W5_SHORT_GI_80 BIT(10) #define MT_WTBL_W5_SHORT_GI_160 BIT(11) #define MT_WTBL_W5_BW_CAP GENMASK(13, 12) +#define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23) +#define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26) +#define MT_WTBL_W5_RATE_IDX GENMASK(31, 29) + #define MT_WTBL_W27_CC_BW_SEL GENMASK(6, 5) #define MT_EFUSE_BASE 0x81070000 |