diff options
| author | Alexandre Courbot <acourbot@nvidia.com> | 2016-11-08 16:50:42 +0900 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-04-05 18:11:46 +0200 |
| commit | 5e91144dd702d068b22a75911c06104e56cb4858 (patch) | |
| tree | ca429915b52d24df6fa74971166552ac7d1ce065 /drivers | |
| parent | bdd2f9cd10eb842be96418cc226bc33744d358b0 (diff) | |
drm/tegra: Add tiling FB modifiers
Add FB modifiers to allow user-space to specify that a surface is in one
of the two tiling formats supported by Tegra chips, and add support in
the tegradrm driver to handle them properly. This is necessary for the
display controller to directly display buffers generated by the GPU.
This feature is intended to replace the dedicated IOCTL enabled
by TEGRA_STAGING and to provide a non-staging alternative to that
solution.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Acked-by: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/tegra/drm.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/tegra/fb.c | 23 |
2 files changed, 22 insertions, 3 deletions
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index 948b529d4097..3f8bd7bd6532 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -164,6 +164,8 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags) drm->mode_config.max_width = 4096; drm->mode_config.max_height = 4096; + drm->mode_config.allow_fb_modifiers = true; + drm->mode_config.funcs = &tegra_drm_mode_funcs; err = tegra_drm_fb_prepare(drm); diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c index f142f6a4db25..d53f49f60b6f 100644 --- a/drivers/gpu/drm/tegra/fb.c +++ b/drivers/gpu/drm/tegra/fb.c @@ -52,9 +52,26 @@ int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer, struct tegra_bo_tiling *tiling) { struct tegra_fb *fb = to_tegra_fb(framebuffer); - - /* TODO: handle YUV formats? */ - *tiling = fb->planes[0]->tiling; + uint64_t modifier = fb->base.modifier; + + switch (fourcc_mod_tegra_mod(modifier)) { + case NV_FORMAT_MOD_TEGRA_TILED: + tiling->mode = TEGRA_BO_TILING_MODE_TILED; + tiling->value = 0; + break; + + case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(0): + tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; + tiling->value = fourcc_mod_tegra_param(modifier); + if (tiling->value > 5) + return -EINVAL; + break; + + default: + /* TODO: handle YUV formats? */ + *tiling = fb->planes[0]->tiling; + break; + } return 0; } |