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authorHuazhong Tan <tanhuazhong@huawei.com>2020-01-11 16:33:51 +0800
committerDavid S. Miller <davem@davemloft.net>2020-01-11 14:52:23 -0800
commit5bb784e973cf35f9883b10bb7b1588616c7ed6b1 (patch)
treef69932aa1b805728d1b3eac08a6438eb228bbf55 /drivers
parentf28368bb4542dbc3c5b6e818211a68cbca6f4d75 (diff)
net: hns3: enlarge HCLGE_RESET_WAIT_CNT
When the load of firmware is high, its reset task may takes more time(which will be as long as 35 seconds). So this patch modifies HCLGE_RESET_WAIT_CNT to match the firmware's. Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
index 89621b587603..d81c97608726 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
@@ -3260,7 +3260,8 @@ static int hclge_notify_roce_client(struct hclge_dev *hdev,
static int hclge_reset_wait(struct hclge_dev *hdev)
{
#define HCLGE_RESET_WATI_MS 100
-#define HCLGE_RESET_WAIT_CNT 200
+#define HCLGE_RESET_WAIT_CNT 350
+
u32 val, reg, reg_bit;
u32 cnt = 0;