diff options
| author | Achiad Shochat <achiad@mellanox.com> | 2015-08-16 16:04:45 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2015-08-17 15:51:35 -0700 |
| commit | 57afead5445de85658e3fa3811ef0cdbf5ed73bf (patch) | |
| tree | d332a7dcee0165609372f133fba32ed5e038c8fd /drivers | |
| parent | 0aa65cc0c2ca7e3908b1e4ae7946d909a4882249 (diff) | |
net/mlx5e: Have a single RSS Toeplitz hash key
No need to generate a unique key per TIR.
Generating a single key per netdev and copying it to all
its TIRs.
Signed-off-by: Achiad Shochat <achiad@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/en.h | 1 | ||||
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 5 |
2 files changed, 5 insertions, 1 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h index e9d7d90363a8..7b2b74398ead 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h @@ -273,6 +273,7 @@ struct mlx5e_params { u32 lro_wqe_sz; u8 rss_hfunc; u16 tx_max_inline; + u8 toeplitz_hash_key[40]; }; enum { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c index 111427b33ec8..662ca675a9ce 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -1611,7 +1611,7 @@ static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt) rx_hash_toeplitz_key); MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); - netdev_rss_key_fill(rss_key, len); + memcpy(rss_key, priv->params.toeplitz_hash_key, len); } break; } @@ -1939,6 +1939,9 @@ static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev, priv->params.default_vlan_prio = 0; priv->params.rss_hfunc = ETH_RSS_HASH_XOR; + netdev_rss_key_fill(priv->params.toeplitz_hash_key, + sizeof(priv->params.toeplitz_hash_key)); + priv->params.lro_en = false && !!MLX5_CAP_ETH(priv->mdev, lro_cap); priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; |