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authorFrederic Barrat <fbarrat@linux.vnet.ibm.com>2016-04-19 18:34:24 +0200
committerMichael Ellerman <mpe@ellerman.id.au>2016-04-22 21:45:50 +1000
commit4aec6ec0da9c72c0fa1a5b0d1133707481347bb3 (patch)
treeea21bd18bfaa947d1163389a5896a2c3a6f68aca /drivers
parente009a7e858fed215cb4eed5174a31cadd42d8797 (diff)
cxl: Increase timeout for detection of AFU mmio hang
PSL designers recommend a larger value for the mmio hang pulse, 256 us instead of 1 us. The CAIA architecture states that it needs to be smaller than 1/2 of the RTOS timeout set in the PHB for outbound non-posted transactions, which is still (easily) the case here. Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Acked-by: Ian Munsie <imunsie@au1.ibm.com> Tested-by: Frank Haverkamp <haver@linux.vnet.ibm.com> Tested-by: Manoj Kumar <manoj@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/misc/cxl/pci.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index c6d5cf5e3793..a08fcc888a71 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -375,8 +375,10 @@ static int init_implementation_adapter_regs(struct cxl *adapter, struct pci_dev
return -ENODEV;
}
+ psl_dsnctl = 0x0000900000000000ULL; /* pteupd ttype, scdone */
+ psl_dsnctl |= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */
/* Tell PSL where to route data to */
- psl_dsnctl = 0x0000900002000000ULL | (chipid << (63-5));
+ psl_dsnctl |= (chipid << (63-5));
psl_dsnctl |= (capp_unit_id << (63-13));
cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);