diff options
| author | Heiner Kallweit <hkallweit1@gmail.com> | 2020-03-01 21:57:08 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2020-03-01 19:06:10 -0800 |
| commit | 48938b1e50270047566025bdc43700e71cc5e6c5 (patch) | |
| tree | bdf56e1d93b8a8d333df80d0379e14e8b3472322 /drivers | |
| parent | 5a8b7c4b7f95c8936cd3dcba01169cd5840e291f (diff) | |
net: phy: mscc: add constants for used interrupt mask bits
Add constants for the used interrupts bits. This avoids the magic
number for MII_VSC85XX_INT_MASK_MASK.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/phy/mscc.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/net/phy/mscc.c b/drivers/net/phy/mscc.c index d24577de0775..b2eac7ee0288 100644 --- a/drivers/net/phy/mscc.c +++ b/drivers/net/phy/mscc.c @@ -80,10 +80,16 @@ enum rgmii_rx_clock_delay { #define MSCC_PHY_EXT_PHY_CNTL_2 24 #define MII_VSC85XX_INT_MASK 25 -#define MII_VSC85XX_INT_MASK_MASK 0xa020 -#define MII_VSC85XX_INT_MASK_WOL 0x0040 +#define MII_VSC85XX_INT_MASK_MDINT BIT(15) +#define MII_VSC85XX_INT_MASK_LINK_CHG BIT(13) +#define MII_VSC85XX_INT_MASK_WOL BIT(6) +#define MII_VSC85XX_INT_MASK_EXT BIT(5) #define MII_VSC85XX_INT_STATUS 26 +#define MII_VSC85XX_INT_MASK_MASK (MII_VSC85XX_INT_MASK_MDINT | \ + MII_VSC85XX_INT_MASK_LINK_CHG | \ + MII_VSC85XX_INT_MASK_EXT) + #define MSCC_PHY_WOL_MAC_CONTROL 27 #define EDGE_RATE_CNTL_POS 5 #define EDGE_RATE_CNTL_MASK 0x00E0 |