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authorThierry Reding <treding@nvidia.com>2015-04-20 14:47:25 +0200
committerThierry Reding <treding@nvidia.com>2016-04-28 12:41:48 +0200
commit3d0f4e5f7a7c9ef2d8504f2b42f9c4d3233ba707 (patch)
tree0cfdef423920ea986eaa0bec6d8892ec741bc0ce /drivers
parent1ec7032ad517714108cc53a6ee7067276ca21e80 (diff)
clk: tegra: Use correct parent for dpaux clock
The dpaux clock is derived from pll_p_out0 (pll_p), not clk_m. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/tegra/clk-tegra-periph.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index 463c114358e6..d758f2169d41 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -821,7 +821,7 @@ static struct tegra_periph_init_data gate_clks[] = {
GATE("ispb", "clk_m", 3, 0, tegra_clk_ispb, 0),
GATE("vim2_clk", "clk_m", 11, 0, tegra_clk_vim2_clk, 0),
GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0),
- GATE("dpaux", "clk_m", 181, 0, tegra_clk_dpaux, 0),
+ GATE("dpaux", "pll_p", 181, 0, tegra_clk_dpaux, 0),
GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0),
GATE("pllg_ref", "pll_ref", 189, 0, tegra_clk_pll_g_ref, 0),
GATE("hsic_trk", "usb2_hsic_trk", 209, TEGRA_PERIPH_NO_RESET, tegra_clk_hsic_trk, 0),