diff options
| author | Tony Prisk <linux@prisktech.co.nz> | 2012-12-27 13:14:29 +1300 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2013-01-15 16:16:23 -0800 |
| commit | 35a5db55ab96eadb07b3d5f7258558c680ebc2f0 (patch) | |
| tree | 0a141c17e7e1342dbf66543a48201a0b9d2f076a /drivers | |
| parent | 3fe296cf5a66a82bc9077865b89075ce813f7f5d (diff) | |
clk: vt8500: Fix error in PLL calculations on non-exact match.
When a PLL frequency calculation is performed and a non-exact match
is found the wrong multiplier and divisors are returned.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/clk-vt8500.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c index fe25570874d6..0cb26bef427d 100644 --- a/drivers/clk/clk-vt8500.c +++ b/drivers/clk/clk-vt8500.c @@ -361,9 +361,9 @@ static void wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate, /* if we got here, it wasn't an exact match */ pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate, rate - best_err); - *multiplier = mul; - *divisor1 = div1; - *divisor2 = div2; + *multiplier = best_mul; + *divisor1 = best_div1; + *divisor2 = best_div2; } static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate, |