diff options
| author | Boris Brezillon <boris.brezillon@free-electrons.com> | 2015-12-02 15:57:20 +0100 |
|---|---|---|
| committer | Boris Brezillon <boris.brezillon@free-electrons.com> | 2016-04-19 22:05:37 +0200 |
| commit | 2d43457f79e48ee427666fdbfe9a53f35d3a1672 (patch) | |
| tree | 5148f96a688dc32ed56a49eebf028c3873a554c8 /drivers | |
| parent | 2f9992e080b8892a10d189cbc846c06e6594ad0b (diff) | |
mtd: nand: sunxi: fix EDO mode selection
The ONFI spec says that EDO should be enabled if the host drives tRC less
than 30ns, but the code just tests for the tRC_min value extracted from
the timings exposed by the NAND chip not the timings actually configured
in the NAND controller.
Fix that by first rounding down the requested clk_rate with
clk_round_rate() and then checking if tRC is actually smaller than 30ns.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mtd/nand/sunxi_nand.c | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c index 05b33035f651..b906fc5a22fe 100644 --- a/drivers/mtd/nand/sunxi_nand.c +++ b/drivers/mtd/nand/sunxi_nand.c @@ -1100,6 +1100,7 @@ static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip, struct sunxi_nfc *nfc = to_sunxi_nfc(chip->nand.controller); u32 min_clk_period = 0; s32 tWB, tADL, tWHR, tRHW, tCAD; + long real_clk_rate; /* T1 <=> tCLS */ if (timings->tCLS_min > min_clk_period) @@ -1197,13 +1198,6 @@ static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip, /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */ chip->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD); - /* - * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data - * output cycle timings shall be used if the host drives tRC less than - * 30 ns. - */ - chip->timing_ctl = (timings->tRC_min < 30000) ? NFC_TIMING_CTL_EDO : 0; - /* Convert min_clk_period from picoseconds to nanoseconds */ min_clk_period = DIV_ROUND_UP(min_clk_period, 1000); @@ -1214,6 +1208,16 @@ static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip, * Allwinner engineers. */ chip->clk_rate = NSEC_PER_SEC / min_clk_period; + real_clk_rate = clk_round_rate(nfc->mod_clk, chip->clk_rate); + + /* + * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data + * output cycle timings shall be used if the host drives tRC less than + * 30 ns. + */ + min_clk_period = NSEC_PER_SEC / real_clk_rate; + chip->timing_ctl = ((min_clk_period * 2) < 30) ? + NFC_TIMING_CTL_EDO : 0; return 0; } |