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authorSeungwon Jeon <tgih.jun@samsung.com>2014-03-14 21:12:38 +0900
committerChris Ball <chris@printf.net>2014-04-20 16:59:56 -0400
commit1a0ae377bf50ed913f2b71b71e3e2cb3fc9eab30 (patch)
tree546db9fea5d1b51c922832e70f86c9fa7dab4d99 /drivers
parent4039ff4741c6e8d27b5ca42dc92d87dc2d625b80 (diff)
mmc: rtsx: clarify DDR timing mode between SD-UHS and eMMC
Added MMC_DDR52 as eMMC's DDR mode is distinguished from SD-UHS. CC: Wei WANG <wei_wang@realsil.com.cn> CC: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/mmc/host/rtsx_pci_sdmmc.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/mmc/host/rtsx_pci_sdmmc.c b/drivers/mmc/host/rtsx_pci_sdmmc.c
index 5fb994f9a653..8c2dd304a7ab 100644
--- a/drivers/mmc/host/rtsx_pci_sdmmc.c
+++ b/drivers/mmc/host/rtsx_pci_sdmmc.c
@@ -1075,6 +1075,7 @@ static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing)
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0);
break;
+ case MMC_TIMING_MMC_DDR52:
case MMC_TIMING_UHS_DDR50:
rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1,
0x0C | SD_ASYNC_FIFO_NOT_RST,
@@ -1155,6 +1156,7 @@ static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
host->vpclk = true;
host->double_clk = false;
break;
+ case MMC_TIMING_MMC_DDR52:
case MMC_TIMING_UHS_DDR50:
case MMC_TIMING_UHS_SDR25:
host->ssc_depth = RTSX_SSC_DEPTH_1M;