diff options
| author | Eric Brower <ebrower@nvidia.com> | 2013-11-18 14:55:06 -0800 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2013-12-07 15:39:06 -0700 |
| commit | 17bd86c69cea4a8364e2ef8a49947dd9d5e26f13 (patch) | |
| tree | 3e0dcdaa40bd1fc7744a5bf0c21158088ba7ea6a /drivers | |
| parent | 6ce4eac1f600b34f2f7f58f9cd8f0503d79e42ae (diff) | |
PCI: Disable Gen2 for Tegra20 and Tegra30
Tegra20 and Tegra30 do not support gen2 PCIe, so correct the
register setting to disable it.
Signed-off-by: Eric Brower <ebrower@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/pci/host/pci-tegra.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 0afbbbc55c81..b8ba2f794559 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -805,7 +805,7 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) afi_writel(pcie, value, AFI_PCIE_CONFIG); value = afi_readl(pcie, AFI_FUSE); - value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; + value |= AFI_FUSE_PCIE_T0_GEN2_DIS; afi_writel(pcie, value, AFI_FUSE); /* initialize internal PHY, enable up to 16 PCIE lanes */ |