diff options
| author | Uma Shankar <uma.shankar@intel.com> | 2019-02-11 19:20:22 +0530 |
|---|---|---|
| committer | Maarten Lankhorst <maarten.lankhorst@linux.intel.com> | 2019-02-13 11:25:24 +0100 |
| commit | 13717cef4c1d627db9ed9288f38893977e4f7eac (patch) | |
| tree | 187b06b940de5b895ff6a690f049d89ebcb4eb2e /drivers | |
| parent | 8957129cb3b0144aceb46b8002cb5d1c45326b01 (diff) | |
drm/i915/icl: Add icl pipe degamma and gamma support
Add support for icl pipe degamma and gamma.
v2: Removed a POSTING_READ and corrected the Bit
Definition as per Maarten's comments.
v3: Addressed Matt's review comments. Removed rmw patterns
as suggested by Matt.
v4: Fixed Matt's review comments.
v5: Corrected macro alignment as per Jani Nikula's comments.
Addressed Ville and Matt's review comments.
v6: Merged ICL degamma handling with GLK and dropped ICL
degamma function as per Ville and Matt's comments.
v7: updated gamma_mode state with pre csc gammma and post
gamma enabling in intel_color_check to align with atomic.
v8: Addressed Maarten's review comments.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1549893025-21837-3-git-send-email-uma.shankar@intel.com
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 12 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_color.c | 21 |
2 files changed, 26 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 11bf60d5e748..13a207a06235 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7111,11 +7111,13 @@ enum { #define _GAMMA_MODE_A 0x4a480 #define _GAMMA_MODE_B 0x4ac80 #define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B) -#define GAMMA_MODE_MODE_MASK (3 << 0) -#define GAMMA_MODE_MODE_8BIT (0 << 0) -#define GAMMA_MODE_MODE_10BIT (1 << 0) -#define GAMMA_MODE_MODE_12BIT (2 << 0) -#define GAMMA_MODE_MODE_SPLIT (3 << 0) +#define PRE_CSC_GAMMA_ENABLE (1 << 31) +#define POST_CSC_GAMMA_ENABLE (1 << 30) +#define GAMMA_MODE_MODE_MASK (3 << 0) +#define GAMMA_MODE_MODE_8BIT (0 << 0) +#define GAMMA_MODE_MODE_10BIT (1 << 0) +#define GAMMA_MODE_MODE_12BIT (2 << 0) +#define GAMMA_MODE_MODE_SPLIT (3 << 0) /* DMC/CSR */ #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index e39189928e10..c5bd0f97e9a8 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -571,6 +571,17 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state) bdw_load_gamma_lut(crtc_state, 0); } +static void icl_load_luts(const struct intel_crtc_state *crtc_state) +{ + glk_load_degamma_lut(crtc_state); + + if (crtc_state_is_legacy_gamma(crtc_state)) + i9xx_load_luts(crtc_state); + else + /* ToDo: Add support for multi segment gamma LUT */ + bdw_load_gamma_lut(crtc_state, 0); +} + static void cherryview_load_luts(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); @@ -760,7 +771,11 @@ int intel_color_check(struct intel_crtc_state *crtc_state) drm_color_lut_check(gamma_lut, gamma_tests)) return -EINVAL; - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) + if (INTEL_GEN(dev_priv) >= 11) + crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT | + PRE_CSC_GAMMA_ENABLE | + POST_CSC_GAMMA_ENABLE; + else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) crtc_state->gamma_mode = GAMMA_MODE_MODE_10BIT; else if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) crtc_state->gamma_mode = GAMMA_MODE_MODE_SPLIT; @@ -784,7 +799,9 @@ void intel_color_init(struct intel_crtc *crtc) dev_priv->display.color_commit = i9xx_color_commit; } else { - if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) + if (IS_ICELAKE(dev_priv)) + dev_priv->display.load_luts = icl_load_luts; + else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) dev_priv->display.load_luts = glk_load_luts; else if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) dev_priv->display.load_luts = broadwell_load_luts; |