diff options
| author | Antoine Ténart <antoine.tenart@free-electrons.com> | 2017-08-22 19:08:22 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2017-08-22 14:32:19 -0700 |
| commit | 1068ec79d9cb5481ccfa6ffacdcf174636227b5d (patch) | |
| tree | 673358af4b3047518975ab551530f763636b7326 /drivers | |
| parent | 81b6630ff7210356fe1843572543c76674e90450 (diff) | |
net: mvpp2: fix the synchronization module bypass macro name
The macro defining the bit to toggle to bypass or not the
synchronization module is wrongly named. Writing 1 will disable bypass.
This patch s/MVPP22_CTRL4_SYNC_BYPASS/MVPP22_CTRL4_SYNC_BYPASS_DIS/.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Tested-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/ethernet/marvell/mvpp2.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c index 34c679f25fec..03b7ced1082f 100644 --- a/drivers/net/ethernet/marvell/mvpp2.c +++ b/drivers/net/ethernet/marvell/mvpp2.c @@ -346,7 +346,7 @@ #define MVPP22_GMAC_CTRL_4_REG 0x90 #define MVPP22_CTRL4_EXT_PIN_GMII_SEL BIT(0) #define MVPP22_CTRL4_DP_CLK_SEL BIT(5) -#define MVPP22_CTRL4_SYNC_BYPASS BIT(6) +#define MVPP22_CTRL4_SYNC_BYPASS_DIS BIT(6) #define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7) /* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0, @@ -4269,7 +4269,7 @@ static void mvpp22_port_mii_set(struct mvpp2_port *port) else val &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL; val &= ~MVPP22_CTRL4_DP_CLK_SEL; - val |= MVPP22_CTRL4_SYNC_BYPASS; + val |= MVPP22_CTRL4_SYNC_BYPASS_DIS; val |= MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; writel(val, port->base + MVPP22_GMAC_CTRL_4_REG); } |