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authorSubhash Jadavani <subhashj@codeaurora.org>2017-01-10 12:30:49 +0530
committerUlf Hansson <ulf.hansson@linaro.org>2017-02-13 13:20:30 +0100
commit083c9aa0ad480af8a4b4b0f6be3bdca847cc211d (patch)
tree844c76358b642126726e40d45752f9f9c62f4a00 /drivers
parent5574ddcc60aaf71372f4f546acfd988ea433f50d (diff)
mmc: sdhci-msm: configure CORE_CSR_CDC_DELAY_CFG to recommended value
Program CORE_CSR_CDC_DELAY_CFG for hardware recommended 1.25ns delay. We may see data CRC errors if it's programmed for any other delay value. Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Tested-by: Jeremy McNicoll <jeremymc@redhat.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/mmc/host/sdhci-msm.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index a028568081a0..84d29dd2cc9e 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -679,7 +679,7 @@ static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
- writel_relaxed(0x3AC, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
+ writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);