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authorGuenter Roeck <linux@roeck-us.net>2017-12-24 13:04:17 -0800
committerWim Van Sebroeck <wim@iguana.be>2018-01-21 12:56:37 +0100
commit887d2ec51e34b704837816a10f185f3b604170fd (patch)
tree80f052d448161a4920b45756838f78c0d4f1e9b5 /drivers/watchdog/sp5100_tco.h
parentf7781b067522aa269213e8025c80cbed1868d349 (diff)
watchdog: sp5100_tco: Add support for recent FCH versions
Starting with Family 16h Models 30h-3Fh and Family 15h Models 60h-6Fh, watchdog address space decoding has changed. The cutover point is already identified in the i2c-piix2 driver, so use the same mechanism. Cc: Zoltán Böszörményi <zboszor@pr.hu> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Diffstat (limited to 'drivers/watchdog/sp5100_tco.h')
-rw-r--r--drivers/watchdog/sp5100_tco.h21
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/watchdog/sp5100_tco.h b/drivers/watchdog/sp5100_tco.h
index 008b2094bd13..87eaf357ae01 100644
--- a/drivers/watchdog/sp5100_tco.h
+++ b/drivers/watchdog/sp5100_tco.h
@@ -62,3 +62,24 @@
#define SB800_PM_WDT_MMIO_OFFSET 0xB00
#define SB800_DEVNAME "SB800 TCO"
+
+/* For recent chips with embedded FCH (rev 40+) */
+
+#define EFCH_PM_DECODEEN 0x00
+
+#define EFCH_PM_DECODEEN_WDT_TMREN BIT(7)
+
+
+#define EFCH_PM_DECODEEN3 0x00
+#define EFCH_PM_DECODEEN_SECOND_RES GENMASK(1, 0)
+#define EFCH_PM_WATCHDOG_DISABLE ((u8)GENMASK(3, 2))
+
+/* WDT MMIO if enabled with PM00_DECODEEN_WDT_TMREN */
+#define EFCH_PM_WDT_ADDR 0xfeb00000
+
+#define EFCH_PM_ISACONTROL 0x04
+
+#define EFCH_PM_ISACONTROL_MMIOEN BIT(1)
+
+#define EFCH_PM_ACPI_MMIO_ADDR 0xfed80000
+#define EFCH_PM_ACPI_MMIO_WDT_OFFSET 0x00000b00