diff options
| author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2011-08-22 13:16:24 +0300 |
|---|---|---|
| committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2011-09-30 16:16:41 +0300 |
| commit | b44e45825dbe30f32c770b98c38555b6bd331760 (patch) | |
| tree | d465a3954443a86e6c0ee1e688b93b78b9c8cbaf /drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | |
| parent | 8d88767a4377171752c22ac39bcb2b505eb751da (diff) | |
OMAP: DSS2: HDMI: change regn definition
regn divider is currently programmed to the registers without change,
but when calculating clock frequencies it is used as regn+1.
To make this similar to how DSI handles the dividers this patch changes
the regn value to be used as such for calculations, but the value
programmed to registers is regn-1.
This simplifies the clock frequency calculations, makes it similar to
DSI, and also allows us to use regn value 0 as undefined.
Cc: Mythri P K <mythripk@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c')
| -rw-r--r-- | drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c index cb3a2d6753de..403c66241477 100644 --- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c +++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c @@ -92,7 +92,7 @@ static int hdmi_pll_init(struct hdmi_ip_data *ip_data) r = hdmi_read_reg(pll_base, PLLCTRL_CFG1); r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */ - r = FLD_MOD(r, fmt->regn, 8, 1); /* CFG1_PLL_REGN */ + r = FLD_MOD(r, fmt->regn - 1, 8, 1); /* CFG1_PLL_REGN */ hdmi_write_reg(pll_base, PLLCTRL_CFG1, r); |