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authorYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>2011-07-08 14:51:27 +0900
committerFelipe Balbi <balbi@ti.com>2011-07-08 12:47:42 +0300
commit5154e9f126c1d2ee8f5f93d9954f83d82b2d5e64 (patch)
tree337df747ff50d9d154509882b704e2ad3ea07d7f /drivers/usb
parentdeafeb24e8a846da8555e68f4bcf651daa8a4ed1 (diff)
usb: gadget: r8a66597-udc: Make BUSWAIT configurable through platform data
BUSWAIT is a 4-bit-wide value that controls the number of access waits from the CPU to on-chip USB module. b'0000 inserts 0 wait (2 access cycles) and b'1111 inserts 15 waits (17 access cycles, hardware initial value), respectively. BUSWAIT value depends on peripheral clock frequency supplied to on-chip of each CPU, hence should be configurable through platform data. Note that this patch assumes that b'0000 (0 wait, 2 access cycles) is rerely used and considered as invalid. If valid 'buswait' data is not provided by platform, initial b'1111 (15 waits, 17 access cycles) will be applied as a safe default. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'drivers/usb')
-rw-r--r--drivers/usb/gadget/r8a66597-udc.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/usb/gadget/r8a66597-udc.c b/drivers/usb/gadget/r8a66597-udc.c
index 4f3f1ce0424b..834a0202ae3f 100644
--- a/drivers/usb/gadget/r8a66597-udc.c
+++ b/drivers/usb/gadget/r8a66597-udc.c
@@ -576,7 +576,11 @@ static void init_controller(struct r8a66597 *r8a66597)
u16 endian = r8a66597->pdata->endian ? BIGEND : 0;
if (r8a66597->pdata->on_chip) {
- r8a66597_bset(r8a66597, 0x04, SYSCFG1);
+ if (r8a66597->pdata->buswait)
+ r8a66597_write(r8a66597, r8a66597->pdata->buswait,
+ SYSCFG1);
+ else
+ r8a66597_write(r8a66597, 0x0f, SYSCFG1);
r8a66597_bset(r8a66597, HSE, SYSCFG0);
r8a66597_bclr(r8a66597, USBE, SYSCFG0);