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authorAaron Sierra <asierra@xes-inc.com>2017-10-04 10:01:28 -0500
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2017-10-20 14:06:45 +0200
commit0ab84da2e076948c49d36197ee7d254125c53eab (patch)
treead91cb3e529c4c808125d0788c2db6cbbb2ba76c /drivers/tty/serial/8250
parent8ffb82094be8ade4f5e60996edcc8afbbcb4f1f4 (diff)
serial: 8250: Preserve DLD[7:4] for PORT_XR17V35X
The upper four bits of the XR17V35x fractional divisor register (DLD) control general chip function (RS-485 direction pin polarity, multidrop mode, XON/XOFF parity check, and fast IR mode). Don't allow these bits to be clobbered when setting the baudrate. Signed-off-by: Aaron Sierra <asierra@xes-inc.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/tty/serial/8250')
-rw-r--r--drivers/tty/serial/8250/8250_port.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
index 01ab2188a151..c2fb92feca20 100644
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -2586,8 +2586,11 @@ static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
serial_dl_write(up, quot);
/* XR17V35x UARTs have an extra fractional divisor register (DLD) */
- if (up->port.type == PORT_XR17V35X)
+ if (up->port.type == PORT_XR17V35X) {
+ /* Preserve bits not related to baudrate; DLD[7:4]. */
+ quot_frac |= serial_port_in(port, 0x2) & 0xf0;
serial_port_out(port, 0x2, quot_frac);
+ }
}
static unsigned int serial8250_get_baud_rate(struct uart_port *port,