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authorSung Lee <sung.lee@amd.com>2020-02-20 15:54:32 -0500
committerAlex Deucher <alexander.deucher@amd.com>2020-03-05 00:30:12 -0500
commit78fe9f63947a2bf5dedc0ece239211edd777c058 (patch)
tree7f154b4ccfe424d6f1be418a2314d1af77942b53 /drivers/tee
parent7bc3807fe1d0694caf59dec983ac5809441cc9ca (diff)
drm/amd/display: Remove DISPCLK Limit Floor for Certain SMU Versions
[WHY] SMU FW previously had an issue with lowering display clock to below 100 MHz, and a workaround was put in to limit it. Newest SMU FW does not have this issue, and no longer needs the 100MHz cap. [HOW] Remove the 100MHz cap based on the SMU FW version. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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