diff options
| author | Matthew Giassa <matthew@giassa.net> | 2017-05-11 18:45:23 -0700 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2017-05-15 07:43:57 +0200 |
| commit | 592a55ef2a2611b2fae2a5e7d43127b5f06eb502 (patch) | |
| tree | c7b851d2eae2723947039053124db9c04a0d32ab /drivers/staging/rtl8723bs/include | |
| parent | 17f858d0799f8242d590a2cb213aab3bb2b8206c (diff) | |
staging: rtl8723bs: checkpatch - fix typos in comments
Resolving checkpatch issue:
CHECK: 'Regsiter' may be misspelled - perhaps 'Register'?
CHECK: 'Interrup' may be misspelled - perhaps 'Interrupt'?
All instances resolved.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/rtl8723bs/include')
| -rw-r--r-- | drivers/staging/rtl8723bs/include/rtl8723b_spec.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/staging/rtl8723bs/include/rtl8723b_spec.h b/drivers/staging/rtl8723bs/include/rtl8723b_spec.h index 1f275a734ea7..1906ff2038f5 100644 --- a/drivers/staging/rtl8723bs/include/rtl8723b_spec.h +++ b/drivers/staging/rtl8723bs/include/rtl8723b_spec.h @@ -141,7 +141,7 @@ #define SDIO_REG_HCPWM1_8723B 0x025 /* HCI Current Power Mode 1 */ /* */ -/* 8723 Regsiter Bit and Content definition */ +/* 8723 Register Bit and Content definition */ /* */ /* 2 HSISR */ @@ -241,13 +241,13 @@ #define IMR_BCNDMAINT3_8723B BIT23 /* Beacon DMA Interrupt 3 */ #define IMR_BCNDMAINT2_8723B BIT22 /* Beacon DMA Interrupt 2 */ #define IMR_BCNDMAINT1_8723B BIT21 /* Beacon DMA Interrupt 1 */ -#define IMR_BCNDOK7_8723B BIT20 /* Beacon Queue DMA OK Interrup 7 */ -#define IMR_BCNDOK6_8723B BIT19 /* Beacon Queue DMA OK Interrup 6 */ -#define IMR_BCNDOK5_8723B BIT18 /* Beacon Queue DMA OK Interrup 5 */ -#define IMR_BCNDOK4_8723B BIT17 /* Beacon Queue DMA OK Interrup 4 */ -#define IMR_BCNDOK3_8723B BIT16 /* Beacon Queue DMA OK Interrup 3 */ -#define IMR_BCNDOK2_8723B BIT15 /* Beacon Queue DMA OK Interrup 2 */ -#define IMR_BCNDOK1_8723B BIT14 /* Beacon Queue DMA OK Interrup 1 */ +#define IMR_BCNDOK7_8723B BIT20 /* Beacon Queue DMA OK Interrupt 7 */ +#define IMR_BCNDOK6_8723B BIT19 /* Beacon Queue DMA OK Interrupt 6 */ +#define IMR_BCNDOK5_8723B BIT18 /* Beacon Queue DMA OK Interrupt 5 */ +#define IMR_BCNDOK4_8723B BIT17 /* Beacon Queue DMA OK Interrupt 4 */ +#define IMR_BCNDOK3_8723B BIT16 /* Beacon Queue DMA OK Interrupt 3 */ +#define IMR_BCNDOK2_8723B BIT15 /* Beacon Queue DMA OK Interrupt 2 */ +#define IMR_BCNDOK1_8723B BIT14 /* Beacon Queue DMA OK Interrupt 1 */ #define IMR_ATIMEND_E_8723B BIT13 /* ATIM Window End Extension for Win7 */ #define IMR_TXERR_8723B BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ #define IMR_RXERR_8723B BIT10 /* Rx Error Flag INT Status, Write 1 clear */ |