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authorSergio Paracuellos <sergio.paracuellos@gmail.com>2021-05-14 13:28:20 +0200
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2021-05-14 13:54:03 +0200
commit519c49678a1311d7ec748660ef1f9d9753970cf1 (patch)
tree1833db981eb97fb4ee8b98a11d6e52274243f30f /drivers/staging/mt7621-dts
parent5f8e9aff1a116c8cc7c58d174d7e2ed172ba8993 (diff)
staging: mt7621-dts: use clock in pci phy nodes
MT7621 SoC clock driver has already mainlined in 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")' Hence we can use the clock in pcie phy nodes to be able to get it from there in driver code. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210514112820.32499-1-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/mt7621-dts')
-rw-r--r--drivers/staging/mt7621-dts/mt7621.dtsi2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
index 9ee11adefa79..840ba0c3ffed 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -548,12 +548,14 @@
pcie0_phy: pcie-phy@1e149000 {
compatible = "mediatek,mt7621-pci-phy";
reg = <0x1e149000 0x0700>;
+ clocks = <&sysc MT7621_CLK_XTAL>;
#phy-cells = <1>;
};
pcie2_phy: pcie-phy@1e14a000 {
compatible = "mediatek,mt7621-pci-phy";
reg = <0x1e14a000 0x0700>;
+ clocks = <&sysc MT7621_CLK_XTAL>;
#phy-cells = <1>;
};
};