diff options
| author | Gregory CLEMENT <gregory.clement@bootlin.com> | 2019-10-17 16:18:40 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2019-10-18 18:26:41 +0100 |
| commit | 4d8672d17450b457c0dbbcfe9868438036b4647c (patch) | |
| tree | f1e69bb39b128fccf4fd77da0612f65aaa103288 /drivers/spi | |
| parent | ae8fbf1d2403bc187a5d8fe82fbf2205d89cdb60 (diff) | |
spi: atmel: Remove and fix erroneous comments
Since CSAAT functionality support has been added. Some comments become
wrong. Fix them to match the current driver behavior.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Link: https://lore.kernel.org/r/20191017141846.7523-2-gregory.clement@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/spi-atmel.c | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c index e34ab587b980..7a17c3e2a8ee 100644 --- a/drivers/spi/spi-atmel.c +++ b/drivers/spi/spi-atmel.c @@ -312,11 +312,9 @@ static bool atmel_spi_is_v2(struct atmel_spi *as) * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer * controllers have CSAAT and friends. * - * Since the CSAAT functionality is a bit weird on newer controllers as - * well, we use GPIO to control nCSx pins on all controllers, updating - * MR.PCS to avoid confusing the controller. Using GPIOs also lets us - * support active-high chipselects despite the controller's belief that - * only active-low devices/systems exists. + * Even controller newer than ar91rm9200, using GPIOs can make sens as + * it lets us support active-high chipselects despite the controller's + * belief that only active-low devices/systems exists. * * However, at91rm9200 has a second erratum whereby nCS0 doesn't work * right when driven with GPIO. ("Mode Fault does not allow more than one @@ -1193,8 +1191,6 @@ static int atmel_spi_setup(struct spi_device *spi) if (!as->use_cs_gpios) csr |= SPI_BIT(CSAAT); - /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs. - */ csr |= SPI_BF(DLYBS, 0); word_delay_csr = atmel_word_delay_csr(spi, as); |