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| author | Brian Norris <briannorris@chromium.org> | 2016-07-14 18:30:59 -0700 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2016-07-20 17:42:47 +0100 |
| commit | 5185a81c02d4118b11e6cb7b5fbf6f15ff7aff90 (patch) | |
| tree | 6eacba8fabd331367a9d99a9eb7b49418d36f74b /drivers/spi/spi-ppc4xx.c | |
| parent | 1a695a905c18548062509178b98bc91e67510864 (diff) | |
spi: rockchip: limit transfers to (64K - 1) bytes
The Rockchip SPI controller's length register only supports 16-bits,
yielding a maximum length of 64KiB (the CTRLR1 register holds "length -
1"). Trying to transfer more than that (e.g., with a large SPI flash
read) will cause the driver to hang.
Now, it seems that while theoretically we should be able to program
CTRLR1 with 0xffff, and get a 64KiB transfer, but that also seems to
cause the core to choke, so stick with a maximum of 64K - 1 bytes --
i.e., 0xffff.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-ppc4xx.c')
0 files changed, 0 insertions, 0 deletions