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| author | Yongqiang Sun <yongqiang.sun@amd.com> | 2020-10-26 12:33:24 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-11-10 14:25:38 -0500 |
| commit | c07cbc1f04ecba00f99e313de3190db5e7438e81 (patch) | |
| tree | de356f48949e4c740b236539cbe607a43ec49b64 /drivers/spi/spi-pic32.c | |
| parent | c6160900239e20d32ee9025fca7d926f8744f448 (diff) | |
drm/amd/display: update dpp dto phase and modulo.
[Why & How]
Program modulo with ref dpp clk Mhz/10.
Program phase with pipe dpp clk Mhz /10.
DMUB FW could use these value to determine optimization clk
for PSR power saving.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/spi/spi-pic32.c')
0 files changed, 0 insertions, 0 deletions