diff options
| author | Fabien Parent <fparent@baylibre.com> | 2021-04-05 22:03:53 +0200 |
|---|---|---|
| committer | Matthias Brugger <matthias.bgg@gmail.com> | 2021-04-06 12:57:10 +0200 |
| commit | 060f7875bd230df1a8f83a988faaee09d693e465 (patch) | |
| tree | ebfe67107f42cce7d0b05b425308f794698e6f3a /drivers/soc/mediatek/mt8167-mmsys.h | |
| parent | e7be7853ab1b82d5b46fd14810995700a3bf3a05 (diff) | |
soc: mediatek: mmsys: Add support for MT8167 SoC
Add routing table for DSI on MT8167 SoC. The registers are mostly
incompatible with the current defines, so new one for MT8167 are added.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Link: https://lore.kernel.org/r/20210405200354.2194930-2-fparent@baylibre.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'drivers/soc/mediatek/mt8167-mmsys.h')
| -rw-r--r-- | drivers/soc/mediatek/mt8167-mmsys.h | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h new file mode 100644 index 000000000000..2772ef5e3934 --- /dev/null +++ b/drivers/soc/mediatek/mt8167-mmsys.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8167_MMSYS_H +#define __SOC_MEDIATEK_MT8167_MMSYS_H + +#define MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x030 +#define MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN 0x038 +#define MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x058 +#define MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN 0x064 +#define MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN 0x06c + +#define MT8167_DITHER_MOUT_EN_RDMA0 0x1 +#define MT8167_RDMA0_SOUT_DSI0 0x2 +#define MT8167_DSI0_SEL_IN_RDMA0 0x1 + +static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = { + { + DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, + MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0, + }, { + DDP_COMPONENT_DITHER, DDP_COMPONENT_RDMA0, + MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0 + }, { + DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, + MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0 + }, { + DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI0, + MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_RDMA0 + }, { + DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI0, + MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_DSI0 + }, +}; + +#endif /* __SOC_MEDIATEK_MT8167_MMSYS_H */ |