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| author | Xi Wang <wangxi11@huawei.com> | 2020-04-28 19:03:39 +0800 |
|---|---|---|
| committer | Jason Gunthorpe <jgg@mellanox.com> | 2020-05-06 17:26:43 -0300 |
| commit | 9b2cf76c9f052987ae5c4ad450ebebdc7c5d7b87 (patch) | |
| tree | b12e04c6037bf9908c0cab707eb546c9ca59bc90 /drivers/regulator/mp8859.c | |
| parent | 5ac55dfc6d92c12d5ef423cd16165eb0350f8f51 (diff) | |
RDMA/hns: Optimize PBL buffer allocation process
PBL table has its own implementation for multi-hop addressing currently,
but for the hardware, all table's addressing use the same logic, there is
no need to implement repeatedly. So optimize the PBL buffer allocation
process by using the mtr's interfaces.
Link: https://lore.kernel.org/r/1588071823-40200-2-git-send-email-liweihang@huawei.com
Signed-off-by: Xi Wang <wangxi11@huawei.com>
Signed-off-by: Lang Cheng <chenglang@huawei.com>
Signed-off-by: Weihang Li <liweihang@huawei.com>
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
Diffstat (limited to 'drivers/regulator/mp8859.c')
0 files changed, 0 insertions, 0 deletions