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authorQipan Li <Qipan.Li@csr.com>2013-07-04 15:55:25 +0800
committerLinus Walleij <linus.walleij@linaro.org>2013-07-22 00:49:36 +0200
commit42a708c9328b1b23ed5f415401975e37a64f2747 (patch)
tree64cabbadf8535c0030773a93944582332ef07848 /drivers/pinctrl
parentc5f167d31530b9b1aa7beb469aeca10f869eff5a (diff)
pinctrl: sirf: fix the pin number and mux bit for usp0
we missed a pin and related mux bit for usp pin group, this patch fixes it. Signed-off-by: Qipan Li <Qipan.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/sirf/pinctrl-atlas6.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pinctrl/sirf/pinctrl-atlas6.c b/drivers/pinctrl/sirf/pinctrl-atlas6.c
index 1fa39a444171..c641be9c5b80 100644
--- a/drivers/pinctrl/sirf/pinctrl-atlas6.c
+++ b/drivers/pinctrl/sirf/pinctrl-atlas6.c
@@ -496,7 +496,7 @@ static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
static const struct sirfsoc_muxmask usp0_muxmask[] = {
{
.group = 1,
- .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
+ .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
},
};
@@ -507,7 +507,7 @@ static const struct sirfsoc_padmux usp0_padmux = {
.funcval = 0,
};
-static const unsigned usp0_pins[] = { 51, 52, 53, 54 };
+static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
static const struct sirfsoc_muxmask usp1_muxmask[] = {
{