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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2020-08-09 12:52:28 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2020-08-09 12:52:28 -0700 |
| commit | 9420f1ce01869409d78901c3e036b2c437cbc6b8 (patch) | |
| tree | ce371cca5922398c811f6a8072aed10343c2594d /drivers/pinctrl/tegra | |
| parent | dec1fbbc1d7c46aed9fc1d3ee1f7f4fc04d6ed51 (diff) | |
| parent | 7ee193e2dda3f48b692fad46ab9df90e99e7b811 (diff) | |
Merge tag 'pinctrl-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of the pin control changes for the v5.9 kernel
series:
Core changes:
- The GPIO patch "gpiolib: Introduce for_each_requested_gpio_in_range()
macro" was put in an immutable branch and merged into the pinctrl
tree as well. We see these changes also here.
- Improved debug output for pins used as GPIO.
New drivers:
- Ocelot Sparx5 SoC driver.
- Intel Emmitsburg SoC subdriver.
- Intel Tiger Lake-H SoC subdriver.
- Qualcomm PM660 SoC subdriver.
- Renesas SH-PFC R8A774E1 subdriver.
Driver improvements:
- Linear improvement and cleanups of the Intel drivers for
Cherryview, Lynxpoint, Baytrail etc. Improved locking among other
things.
- Renesas SH-PFC has added support for RPC pins, groups, and
functions to r8a77970 and r8a77980.
- The newere Freescale (now NXP) i.MX8 pin controllers have been
modularized. This is driven by the Google Android GKI initiative I
think.
- Open drain support for pins on the Qualcomm IPQ4019.
- The Ingenic driver can handle both edges IRQ detection.
- A big slew of documentation fixes all over the place.
- A few irqchip template conversions by yours truly.
* tag 'pinctrl-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (107 commits)
dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
pinctrl: stmfx: Use irqchip template
pinctrl: amd: Use irqchip template
pinctrl: mediatek: fix build for tristate changes
pinctrl: samsung: Use bank name as irqchip name
pinctrl: core: print gpio in pins debugfs file
pinctrl: mediatek: add mt6779 eint support
pinctrl: mediatek: add pinctrl support for MT6779 SoC
pinctrl: mediatek: avoid virtual gpio trying to set reg
pinctrl: mediatek: update pinmux definitions for mt6779
pinctrl: stm32: use the hwspin_lock_timeout_in_atomic() API
pinctrl: mcp23s08: Use irqchip template
pinctrl: sx150x: Use irqchip template
dt-bindings: ingenic,pinctrl: Support pinmux/pinconf nodes
pinctrl: intel: Add Intel Emmitsburg pin controller support
pinctl: ti: iodelay: Replace HTTP links with HTTPS ones
Revert "gpio: omap: handle pin config bias flags"
pinctrl: single: Use fallthrough pseudo-keyword
pinctrl: qcom: spmi-gpio: Use fallthrough pseudo-keyword
pinctrl: baytrail: Use fallthrough pseudo-keyword
...
Diffstat (limited to 'drivers/pinctrl/tegra')
| -rw-r--r-- | drivers/pinctrl/tegra/pinctrl-tegra194.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra194.c b/drivers/pinctrl/tegra/pinctrl-tegra194.c index 2e0b5f7bb095..c94ba17243c8 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra194.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra194.c @@ -98,7 +98,6 @@ static struct tegra_function tegra194_functions[] = { .sfsel_bit = 10, \ .schmitt_bit = schmitt_b, \ .drvtype_bit = 13, \ - .drv_reg = -1, \ .parked_bitmask = 0 #define drive_pex_l5_clkreq_n_pgg0 \ |