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authorStephen Warren <swarren@nvidia.com>2015-02-24 14:00:48 -0700
committerLinus Walleij <linus.walleij@linaro.org>2015-03-09 18:10:57 +0100
commit8d4684b39b5865ef5471a256adfcd8d7c3e18d43 (patch)
tree736e56c1c3b1cd0f1d59c0e300fdf380788ffd74 /drivers/pinctrl/pinctrl-tegra114.c
parentb5eec4d061cad4a084c05c7dadd6884fd5fe0df9 (diff)
pinctrl: tegra: driver layout/consistency fixes
Various non-semantic tweaks and layout/consistency fixes for existing Tegra pinctrl drivers. Move the definition of DRV_PINGROUP_REG() before the definition of PINGROUP() so that a future SoC driver can invoke the former from the latter. PINGROUP_BIT_Y(n) is just n, so replace it with n. Re-wrap the parameters to *PINGROUP(). Keep various enums sorted in the Tegra124 driver. Various white-space consistency fixes. These changes aim to update existing drivers to be consistent with future SoC drivers. While we could ignore these tweaks to the existing drivers, I'd like to keep everything as consistent as possible for easy comparison. Besides, I auto-generate the drivers, and maintaining special-cases to keep the differences in place is annoying. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/pinctrl-tegra114.c')
-rw-r--r--drivers/pinctrl/pinctrl-tegra114.c14
1 files changed, 6 insertions, 8 deletions
diff --git a/drivers/pinctrl/pinctrl-tegra114.c b/drivers/pinctrl/pinctrl-tegra114.c
index 52e4ec6386b4..0740cdba7508 100644
--- a/drivers/pinctrl/pinctrl-tegra114.c
+++ b/drivers/pinctrl/pinctrl-tegra114.c
@@ -1547,6 +1547,7 @@ static struct tegra_function tegra114_functions[] = {
#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
#define PINGROUP_REG_A 0x3000 /* bank 1 */
+#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
#define PINGROUP_BIT_Y(b) (b)
@@ -1572,20 +1573,17 @@ static struct tegra_function tegra114_functions[] = {
.tri_reg = PINGROUP_REG(r), \
.tri_bank = 1, \
.tri_bit = 4, \
- .einput_bit = PINGROUP_BIT_Y(5), \
+ .einput_bit = 5, \
.odrain_bit = PINGROUP_BIT_##od(6), \
- .lock_bit = PINGROUP_BIT_Y(7), \
+ .lock_bit = 7, \
.ioreset_bit = PINGROUP_BIT_##ior(8), \
.rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \
.drv_reg = -1, \
}
-#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
-
-#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
- drvdn_b, drvdn_w, drvup_b, drvup_w, \
- slwr_b, slwr_w, slwf_b, slwf_w, \
- drvtype) \
+#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
+ drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \
+ slwf_b, slwf_w, drvtype) \
{ \
.name = "drive_" #pg_name, \
.pins = drive_##pg_name##_pins, \