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| author | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 2015-06-09 18:47:07 +0200 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2015-06-10 11:11:39 +0200 |
| commit | 5cc0de1faff6ac801286dfab88e4a31392cbb3f0 (patch) | |
| tree | 455542fe5a00446773556309453ed9fc466b171c /drivers/pinctrl/mvebu/pinctrl-armada-38x.c | |
| parent | 7bd6a26db6f9dade7dbd88a73120d17da1ee0e89 (diff) | |
pinctrl: mvebu: armada-39x: align NAND pin naming
All SoCs use "nand" to designate NAND pins, only Armada 39x is using
"nd", which is not consistent. This commit fixes that by renaming the
corresponding functions.
It also changes the subnames from rbn0/rbn1 to rb0/rb1, to respect the
convention used everywhere that we don't encode the 'n' part of signal
names.
While this commit changes the main name of function, therefore
potentially breaking the DT compatibility, this is not a problem since
Armada 39x is a brand new SoC which isn't used in production yet.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/mvebu/pinctrl-armada-38x.c')
0 files changed, 0 insertions, 0 deletions