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authorIan Munsie <imunsie@au1.ibm.com>2016-07-01 02:50:40 +1000
committerMichael Ellerman <mpe@ellerman.id.au>2016-07-08 22:11:18 +1000
commit5e7823c9bc44965c2e7d1d755b382109830c4916 (patch)
tree3ba0f08a052e088deca0e138fce3b1cc53ce6d80 /drivers/phy/phy-omap-control.c
parent2224b6719b09052a9fbf29422a0e9b4f42407c35 (diff)
cxl: Fix bug where AFU disable operation had no effect
The AFU disable operation has a bug where it will not clear the enable bit and therefore will have no effect. To date this has likely been masked by fact that we perform an AFU reset before the disable, which also has the effect of clearing the enable bit, making the following disable operation effectively a noop on most hardware. This patch modifies the afu_control function to take a parameter to clear from the AFU control register so that the disable operation can clear the appropriate bit. This bug was uncovered on the Mellanox CX4, which uses an XSL rather than a PSL. On the XSL the reset operation will not complete while the AFU is enabled, meaning the enable bit was still set at the start of the disable and as a result this bug was hit and the disable also timed out. Because of this difference in behaviour between the PSL and XSL, this patch now makes the reset dependent on the card using a PSL to avoid waiting for a timeout on the XSL. It is entirely possible that we may be able to drop the reset altogether if it turns out we only ever needed it due to this bug - however I am not willing to drop it without further regression testing and have added comments to the code explaining the background. This also fixes a small issue where the AFU_Cntl register was read outside of the lock that protects it. Signed-off-by: Ian Munsie <imunsie@au1.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'drivers/phy/phy-omap-control.c')
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