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authorKishon Vijay Abraham I <kishon@ti.com>2021-03-19 18:11:27 +0530
committerVinod Koul <vkoul@kernel.org>2021-03-31 16:43:21 +0530
commit28081b72859f0fa3d5b56cfd84b2f5ba578765d2 (patch)
tree79304aaaab9c7c871f79771c9bfafb630f1dac59 /drivers/phy/cadence/Kconfig
parentdb7a346405dc71be0c4ad7f39dd7978d4d20dee0 (diff)
phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as clocks so that it's possible to select one of these two inputs from device tree. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210319124128.13308-13-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy/cadence/Kconfig')
-rw-r--r--drivers/phy/cadence/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig
index 27e9d6c377e5..a62910ff5591 100644
--- a/drivers/phy/cadence/Kconfig
+++ b/drivers/phy/cadence/Kconfig
@@ -25,6 +25,7 @@ config PHY_CADENCE_DPHY
config PHY_CADENCE_SIERRA
tristate "Cadence Sierra PHY Driver"
depends on OF && HAS_IOMEM && RESET_CONTROLLER
+ depends on COMMON_CLK
select GENERIC_PHY
help
Enable this to support the Cadence Sierra PHY driver