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authorNiklas Cassel <niklas.cassel@axis.com>2018-03-28 13:50:11 +0200
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2018-04-03 12:33:08 +0100
commitd28810ba7891a1df2cb00116c6c66167970a193d (patch)
tree5a15f23ae612185b7b13258c23673086b47cc525 /drivers/pci
parentf25b5fae29d4e5fe6ae17d3f898a959d72519b6a (diff)
PCI: designware-ep: Make dw_pcie_ep_set_bar() handle 64-bit BARs properly
Since a 64-bit BAR consists of a BAR pair, we need to write to both BARs in the BAR pair to setup the BAR properly. Link: https://lkml.kernel.org/r/20180328115018.31921-7-niklas.cassel@axis.com Signed-off-by: Niklas Cassel <niklas.cassel@axis.com> [lorenzo.pieralisi@arm.com: updated code according to review] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/dwc/pcie-designware-ep.c9
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c
index b3a5533fe0b9..70c8c1eedb42 100644
--- a/drivers/pci/dwc/pcie-designware-ep.c
+++ b/drivers/pci/dwc/pcie-designware-ep.c
@@ -138,8 +138,15 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
return ret;
dw_pcie_dbi_ro_wr_en(pci);
- dw_pcie_writel_dbi2(pci, reg, size - 1);
+
+ dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1));
dw_pcie_writel_dbi(pci, reg, flags);
+
+ if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
+ dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1));
+ dw_pcie_writel_dbi(pci, reg + 4, 0);
+ }
+
dw_pcie_dbi_ro_wr_dis(pci);
return 0;