diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2018-03-09 14:13:42 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2018-03-16 10:56:03 +0100 |
| commit | bb9d812643d8a121df7d614a2b9c60193a92deb0 (patch) | |
| tree | 419096f57ca0501d8813151a5236387074edb4ea /drivers/pci | |
| parent | 4ba66a9760722ccbb691b8f7116cad2f791cca7b (diff) | |
arch: remove tile port
The Tile architecture port was added by Chris Metcalf in 2010, and
maintained until early 2018 when he orphaned it due to his departure
from Mellanox, and nobody else stepped up to maintain it. The product
line is still around in the form of the BlueField SoC, but no longer
uses the Tile architecture.
There are also still products for sale with Tile-GX SoCs, notably the
Mikrotik CCR router family. The products all use old (linux-3.3) kernels
with lots of patches and won't be upgraded by their manufacturers. There
have been efforts to port both OpenWRT and Debian to these, but both
projects have stalled and are very unlikely to be continued in the future.
Given that we are reasonably sure that nobody is still using the port
with an upstream kernel any more, it seems better to remove it now while
the port is in a good shape than to let it bitrot for a few years first.
Cc: Chris Metcalf <chris.d.metcalf@gmail.com>
Cc: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
Link: http://www.mellanox.com/page/npu_multicore_overview
Link: https://jenkins.debian.net/view/rebootstrap/job/rebootstrap_tilegx_gcc7/
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/quirks.c | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 8b14bd326d4a..5b997138e092 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2319,25 +2319,6 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, quirk_unhide_mch_dev6); -#ifdef CONFIG_TILEPRO -/* - * The Tilera TILEmpower tilepro platform needs to set the link speed - * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed - * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe - * capability register of the PEX8624 PCIe switch. The switch - * supports link speed auto negotiation, but falsely sets - * the link speed to 5GT/s. - */ -static void quirk_tile_plx_gen1(struct pci_dev *dev) -{ - if (tile_plx_gen1) { - pci_write_config_dword(dev, 0x98, 0x1); - mdelay(50); - } -} -DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1); -#endif /* CONFIG_TILEPRO */ - #ifdef CONFIG_PCI_MSI /* Some chipsets do not support MSI. We cannot easily rely on setting * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually |