diff options
author | Bjorn Helgaas <bhelgaas@google.com> | 2020-10-21 09:58:43 -0500 |
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committer | Bjorn Helgaas <bhelgaas@google.com> | 2020-10-21 09:58:43 -0500 |
commit | 3b353982202be8ac36aab1636c365e02f8dd46a0 (patch) | |
tree | be28a2cecdb6692b5c14dff58dc3760acd749f18 /drivers/pci | |
parent | be36e9b97144206a30a85ceb920b6f90c3595afd (diff) | |
parent | d3d4d028afb785e52c55024d779089654f8302e7 (diff) |
Merge branch 'remotes/lorenzo/pci/qcom'
- Make sure PCIe is reset before init to work around QSDK U-Boot issue
(Ansuel Smith)
- Set iproc affinity mask on MSI interrupts (Mark Tomlinson)
* remotes/lorenzo/pci/qcom:
PCI: qcom: Make sure PCIe is reset before init for rev 2.1.0
Diffstat (limited to 'drivers/pci')
-rw-r--r-- | drivers/pci/controller/dwc/pcie-qcom.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 5eb28251dbee..b4761640ffd9 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -297,6 +297,9 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) reset_control_assert(res->por_reset); reset_control_assert(res->ext_reset); reset_control_assert(res->phy_reset); + + writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL); + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } @@ -309,6 +312,16 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) u32 val; int ret; + /* reset the PCIe interface as uboot can leave it undefined state */ + reset_control_assert(res->pci_reset); + reset_control_assert(res->axi_reset); + reset_control_assert(res->ahb_reset); + reset_control_assert(res->por_reset); + reset_control_assert(res->ext_reset); + reset_control_assert(res->phy_reset); + + writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL); + ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); if (ret < 0) { dev_err(dev, "cannot enable regulators\n"); |