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authorHeiner Kallweit <hkallweit1@gmail.com>2020-12-08 18:57:02 +0100
committerBjorn Helgaas <bhelgaas@google.com>2020-12-08 16:38:32 -0600
commit0aec75a5963e8d72c59a42055c5b5c524893b910 (patch)
tree63cfd70503e21695049302bb367d0f58812092ee /drivers/pci
parentb577562ccc072ab4b09243740ebeca52309eecd2 (diff)
PCI: Reduce pci_set_cacheline_size() message to debug level
Drivers like ehci_hcd and xhci_hcd use pci_set_mwi() and emit an annnoying message like the following that results in user questions whether something is broken: xhci_hcd 0000:00:15.0: cache line size of 64 is not supported Root cause of the message is that on several chips the Cache Line Size register is hard-wired to 0. Change this message to debug level; an interested caller can still inform the user (if deemed helpful) based on the return code. Link: https://lore.kernel.org/r/be1ed3a2-98b9-ee1d-20b8-477f3d93961d@gmail.com Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/pci.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index dd4bbb699abd..556fb5e00d86 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4317,7 +4317,7 @@ int pci_set_cacheline_size(struct pci_dev *dev)
if (cacheline_size == pci_cache_line_size)
return 0;
- pci_info(dev, "cache line size of %d is not supported\n",
+ pci_dbg(dev, "cache line size of %d is not supported\n",
pci_cache_line_size << 2);
return -EINVAL;