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authorGabriele Paoloni <gabriele.paoloni@huawei.com>2015-09-29 00:03:10 +0800
committerBjorn Helgaas <bhelgaas@google.com>2015-11-02 14:48:45 -0600
commit907fce0902539ecde609e485eb2ecd7119a7a623 (patch)
tree158e8616fa813e0d0e2aa9a285f9de0f22317143 /drivers/pci/host
parentb6b18f589e1ddbfbc31f72ea7fb8a723a2d10058 (diff)
PCI: designware: Make "num-lanes" an optional DT property
Currently "num-lanes" is read in dw_pcie_host_init(), but it is only used if we call dw_pcie_setup_rc() while bringing up the link. If the link has already been brought up by firmware, we need not call dw_pcie_setup_rc(), and "num-lanes" is unnecessary. Only complain about "num-lanes" if we actually need it and we didn't find a valid value. [bhelgaas: changelog] Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci/host')
-rw-r--r--drivers/pci/host/pcie-designware.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index b77535f3967b..fb89ca23d9a8 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -534,10 +534,9 @@ int dw_pcie_host_init(struct pcie_port *pp)
}
}
- if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {
- dev_err(pp->dev, "Failed to parse the number of lanes\n");
- return -EINVAL;
- }
+ ret = of_property_read_u32(np, "num-lanes", &pp->lanes);
+ if (ret)
+ pp->lanes = 0;
if (IS_ENABLED(CONFIG_PCI_MSI)) {
if (!pp->ops->msi_host_init) {
@@ -814,6 +813,9 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
case 8:
val |= PORT_LINK_MODE_8_LANES;
break;
+ default:
+ dev_err(pp->dev, "num-lanes %u: invalid value\n", pp->lanes);
+ return;
}
dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);