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authorKishon Vijay Abraham I <kishon@ti.com>2017-03-13 19:13:26 +0530
committerBjorn Helgaas <bhelgaas@google.com>2017-04-04 08:40:55 -0500
commita509d7d9af5ebf86ffbefa98e49761d813fb1d40 (patch)
tree7dc1c06d9aab039477a65b0d28464e2b88a9a6dd /drivers/pci/dwc/pcie-designware.h
parentb50b2db266d8a8c303e8d88590c6416dfe576c6c (diff)
PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes
Previously dbi accessors can be used to access data of size 4 bytes. But there might be situations (like accessing MSI_MESSAGE_CONTROL in order to set/get the number of required MSI interrupts in EP mode) where dbi accessors must be used to access data of size 2. This is in preparation for adding endpoint mode support to designware driver. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Niklas Cassel <niklas.cassel@axis.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com>
Diffstat (limited to 'drivers/pci/dwc/pcie-designware.h')
-rw-r--r--drivers/pci/dwc/pcie-designware.h18
1 files changed, 10 insertions, 8 deletions
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index 09b334a12892..bfaf2b850a88 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -144,9 +144,10 @@ struct pcie_port {
struct dw_pcie_ops {
u64 (*cpu_addr_fixup)(u64 cpu_addr);
- u32 (*readl_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg);
- void (*writel_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
- u32 val);
+ u32 (*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
+ size_t size);
+ void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
+ size_t size, u32 val);
int (*link_up)(struct dw_pcie *pcie);
};
@@ -164,9 +165,10 @@ struct dw_pcie {
int dw_pcie_read(void __iomem *addr, int size, u32 *val);
int dw_pcie_write(void __iomem *addr, int size, u32 val);
-u32 __dw_pcie_readl_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg);
-void __dw_pcie_writel_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
- u32 val);
+u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
+ size_t size);
+void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
+ size_t size, u32 val);
int dw_pcie_link_up(struct dw_pcie *pci);
int dw_pcie_wait_for_link(struct dw_pcie *pci);
void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
@@ -176,12 +178,12 @@ void dw_pcie_setup(struct dw_pcie *pci);
static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
{
- __dw_pcie_writel_dbi(pci, pci->dbi_base, reg, val);
+ __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, val);
}
static inline u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
{
- return __dw_pcie_readl_dbi(pci, pci->dbi_base, reg);
+ return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x4);
}
#ifdef CONFIG_PCIE_DW_HOST