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authorBjorn Helgaas <bhelgaas@google.com>2021-01-26 15:35:03 -0600
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2021-01-28 10:46:43 +0000
commitcc4a08cd09e4766066eee86ce501fbed42d8ff75 (patch)
treed422542dd5ea62b529d97c9d2d49aa76815cd4bb /drivers/pci/controller
parent5ce6697a4460d06d4ea3ec8347974176591e1694 (diff)
PCI: xgene: Fix CRS SV comment
Configuration Request Retry Status ("CRS") must be supported by all PCIe devices. CRS Software Visibility is an optional feature that enables a Root Port to make CRS visible to software by returning a special data value to complete a config read. Clarify a comment to say that it is "CRS SV", not "CRS", that can be enabled. Link: https://lore.kernel.org/r/20210126213503.2922848-1-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Diffstat (limited to 'drivers/pci/controller')
-rw-r--r--drivers/pci/controller/pci-xgene.c13
1 files changed, 7 insertions, 6 deletions
diff --git a/drivers/pci/controller/pci-xgene.c b/drivers/pci/controller/pci-xgene.c
index 85e7c98265e8..2afdc865253e 100644
--- a/drivers/pci/controller/pci-xgene.c
+++ b/drivers/pci/controller/pci-xgene.c
@@ -173,12 +173,13 @@ static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
/*
* The v1 controller has a bug in its Configuration Request
- * Retry Status (CRS) logic: when CRS is enabled and we read the
- * Vendor and Device ID of a non-existent device, the controller
- * fabricates return data of 0xFFFF0001 ("device exists but is not
- * ready") instead of 0xFFFFFFFF ("device does not exist"). This
- * causes the PCI core to retry the read until it times out.
- * Avoid this by not claiming to support CRS.
+ * Retry Status (CRS) logic: when CRS Software Visibility is
+ * enabled and we read the Vendor and Device ID of a non-existent
+ * device, the controller fabricates return data of 0xFFFF0001
+ * ("device exists but is not ready") instead of 0xFFFFFFFF
+ * ("device does not exist"). This causes the PCI core to retry
+ * the read until it times out. Avoid this by not claiming to
+ * support CRS SV.
*/
if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&
((where & ~0x3) == XGENE_V1_PCI_EXP_CAP + PCI_EXP_RTCTL))