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| author | Bjorn Helgaas <bhelgaas@google.com> | 2021-07-06 10:56:26 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2021-07-06 10:56:26 -0500 |
| commit | 364a716bd73e9846d3118a43f600f8f517658b38 (patch) | |
| tree | 76e6c3d257b9a54a5385c458b925f9530dcbc845 /drivers/pci/controller/dwc/pcie-intel-gw.c | |
| parent | 570987cb4c4d5fea2270ea646657376f5a7369e4 (diff) | |
| parent | 655832d12f2251e04031294f547c86935a0a126d (diff) | |
Merge branch 'pci/host/intel-gw'
- Fix INTx enable (Martin Blumenstingl)
* pci/host/intel-gw:
PCI: intel-gw: Fix INTx enable
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-intel-gw.c')
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-intel-gw.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c index f89a7d24ba28..d15cf35fa7f2 100644 --- a/drivers/pci/controller/dwc/pcie-intel-gw.c +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c @@ -39,6 +39,10 @@ #define PCIE_APP_IRN_PM_TO_ACK BIT(9) #define PCIE_APP_IRN_LINK_AUTO_BW_STAT BIT(11) #define PCIE_APP_IRN_BW_MGT BIT(12) +#define PCIE_APP_IRN_INTA BIT(13) +#define PCIE_APP_IRN_INTB BIT(14) +#define PCIE_APP_IRN_INTC BIT(15) +#define PCIE_APP_IRN_INTD BIT(16) #define PCIE_APP_IRN_MSG_LTR BIT(18) #define PCIE_APP_IRN_SYS_ERR_RC BIT(29) #define PCIE_APP_INTX_OFST 12 @@ -48,10 +52,8 @@ PCIE_APP_IRN_RX_VDM_MSG | PCIE_APP_IRN_SYS_ERR_RC | \ PCIE_APP_IRN_PM_TO_ACK | PCIE_APP_IRN_MSG_LTR | \ PCIE_APP_IRN_BW_MGT | PCIE_APP_IRN_LINK_AUTO_BW_STAT | \ - (PCIE_APP_INTX_OFST + PCI_INTERRUPT_INTA) | \ - (PCIE_APP_INTX_OFST + PCI_INTERRUPT_INTB) | \ - (PCIE_APP_INTX_OFST + PCI_INTERRUPT_INTC) | \ - (PCIE_APP_INTX_OFST + PCI_INTERRUPT_INTD)) + PCIE_APP_IRN_INTA | PCIE_APP_IRN_INTB | \ + PCIE_APP_IRN_INTC | PCIE_APP_IRN_INTD) #define BUS_IATU_OFFSET SZ_256M #define RESET_INTERVAL_MS 100 |