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authorGanesh Goudar <ganeshgr@chelsio.com>2017-05-31 19:10:21 +0530
committerDavid S. Miller <davem@davemloft.net>2017-06-02 14:07:14 -0400
commita97051f4553551d13e586ab3cb6ae13093a44a81 (patch)
treebc54f58665f1b75e60939c6289ead5b6e02b26a3 /drivers/net
parent91a09e0c77d5462706c3f44178a7eb3dd0e9804e (diff)
cxgb4: fix incorrect cim_la output for T6
take care of UpDbgLaRdPtr[0-3] restriction for T6. Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4_hw.c11
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
index 9160c882fbfc..822c560fb310 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
@@ -8312,7 +8312,16 @@ int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
if (ret)
break;
- idx = (idx + 1) & UPDBGLARDPTR_M;
+
+ /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
+ * identify the 32-bit portion of the full 312-bit data
+ */
+ if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
+ idx = (idx & 0xff0) + 0x10;
+ else
+ idx++;
+ /* address can't exceed 0xfff */
+ idx &= UPDBGLARDPTR_M;
}
restart:
if (cfg & UPDBGLAEN_F) {