diff options
| author | Tariq Toukan <tariqt@mellanox.com> | 2018-12-16 17:20:31 +0200 |
|---|---|---|
| committer | Saeed Mahameed <saeedm@mellanox.com> | 2019-04-05 14:10:35 -0700 |
| commit | 98df6d5b877c26012bbafcf07ff51326db4ef3f7 (patch) | |
| tree | 390631e1606bc0a74d9c7525863af26741fb5014 /drivers/net | |
| parent | 27c11b6b844cd9473330ff29ddb55a535d2dd14a (diff) | |
net/mlx5: A write memory barrier is sufficient in EQ ci update
Soften the memory barrier call of mb() by a sufficient wmb() in the
consumer index update of the event queues.
Signed-off-by: Tariq Toukan <tariqt@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlx5/core/eq.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eq.c b/drivers/net/ethernet/mellanox/mlx5/core/eq.c index 46a747f7c162..e9837aeb7088 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c @@ -707,7 +707,7 @@ void mlx5_eq_update_ci(struct mlx5_eq *eq, u32 cc, bool arm) __raw_writel((__force u32)cpu_to_be32(val), addr); /* We still want ordering, just not swabbing, so add a barrier */ - mb(); + wmb(); } EXPORT_SYMBOL(mlx5_eq_update_ci); |