diff options
| author | Felix Fietkau <nbd@nbd.name> | 2020-08-07 19:31:40 +0200 |
|---|---|---|
| committer | Felix Fietkau <nbd@nbd.name> | 2020-09-24 18:10:14 +0200 |
| commit | 40fde8c486950d03eb1ed76802c4e5a41ad94421 (patch) | |
| tree | dc361c30e54da96a41b21c7794e759f623681213 /drivers/net/wireless/mediatek | |
| parent | acc4696dcfea8d6ed5a3748467580ca3228dde00 (diff) | |
mt76: mt7615: only clear unmasked interrupts in irq tasklet
If an interrupt is temporarily masked, its pending events need to be processed
later, even if another interrupt happened in the mean time.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Diffstat (limited to 'drivers/net/wireless/mediatek')
| -rw-r--r-- | drivers/net/wireless/mediatek/mt76/mt7615/mmio.c | 19 |
1 files changed, 8 insertions, 11 deletions
diff --git a/drivers/net/wireless/mediatek/mt76/mt7615/mmio.c b/drivers/net/wireless/mediatek/mt76/mt7615/mmio.c index a0526f06262b..99ece641bdef 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7615/mmio.c +++ b/drivers/net/wireless/mediatek/mt76/mt7615/mmio.c @@ -106,25 +106,24 @@ static void mt7615_irq_tasklet(unsigned long data) mt76_wr(dev, MT_INT_MASK_CSR, 0); intr = mt76_rr(dev, MT_INT_SOURCE_CSR); + intr &= dev->mt76.mmio.irqmask; mt76_wr(dev, MT_INT_SOURCE_CSR, intr); trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); - intr &= dev->mt76.mmio.irqmask; - if (intr & MT_INT_TX_DONE_ALL) { + mask |= intr & MT_INT_RX_DONE_ALL; + if (intr & MT_INT_TX_DONE_ALL) mask |= MT_INT_TX_DONE_ALL; + mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0); + + if (intr & MT_INT_TX_DONE_ALL) napi_schedule(&dev->mt76.tx_napi); - } - if (intr & MT_INT_RX_DONE(0)) { - mask |= MT_INT_RX_DONE(0); + if (intr & MT_INT_RX_DONE(0)) napi_schedule(&dev->mt76.napi[0]); - } - if (intr & MT_INT_RX_DONE(1)) { - mask |= MT_INT_RX_DONE(1); + if (intr & MT_INT_RX_DONE(1)) napi_schedule(&dev->mt76.napi[1]); - } if (intr & MT_INT_MCU_CMD) { u32 val = mt76_rr(dev, MT_MCU_CMD); @@ -135,8 +134,6 @@ static void mt7615_irq_tasklet(unsigned long data) wake_up(&dev->reset_wait); } } - - mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0); } static u32 __mt7615_reg_addr(struct mt7615_dev *dev, u32 addr) |