diff options
| author | Martin Fuzzey <martin.fuzzey@flowbird.group> | 2019-10-23 11:44:24 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2019-10-23 21:44:44 -0700 |
| commit | 76db2d466f6a929a04775f0f87d837e3bcba44e8 (patch) | |
| tree | 1c6e3bfb52d93fc25ea06992920c6ae17330f8e8 /drivers/net/phy | |
| parent | 55667441c84fa5e0911a0aac44fb059c15ba6da2 (diff) | |
net: phy: smsc: LAN8740: add PHY_RST_AFTER_CLK_EN flag
The LAN8740, like the 8720, also requires a reset after enabling clock.
The datasheet [1] 3.8.5.1 says:
"During a Hardware reset, an external clock must be supplied
to the XTAL1/CLKIN signal."
I have observed this issue on a custom i.MX6 based board with
the LAN8740A.
[1] http://ww1.microchip.com/downloads/en/DeviceDoc/8740a.pdf
Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/phy')
| -rw-r--r-- | drivers/net/phy/smsc.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c index dc3d92d340c4..b73298250793 100644 --- a/drivers/net/phy/smsc.c +++ b/drivers/net/phy/smsc.c @@ -327,6 +327,7 @@ static struct phy_driver smsc_phy_driver[] = { .name = "SMSC LAN8740", /* PHY_BASIC_FEATURES */ + .flags = PHY_RST_AFTER_CLK_EN, .probe = smsc_phy_probe, |